Commit Graph

18 Commits

Author SHA1 Message Date
Mikko Perttunen
15274c2321 arm64: tegra: Add BPMP thermal sensor to Tegra186
This adds the thermal sensor device provided by the BPMP, and the
relevant thermal sensors to the Tegra186 device tree.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-19 16:35:50 +02:00
Manikanta Maddireddy
f8973cf43c arm64: tegra: Add PCIe node for Tegra186
Tegra186 has three PCIe controllers, which can be operated
in 401, 211 or 111 lane combinations. Add DT support for
PCIe controllers.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-19 16:35:49 +02:00
Mikko Perttunen
effc4b44e0 arm64: tegra: Add VIC on Tegra186
Add a node for the Video Image Compositor on the Tegra186.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-19 16:35:49 +02:00
Mikko Perttunen
5524c61fba arm64: tegra: Add host1x on Tegra186
Add the node for Host1x on the Tegra186, without any subdevices
for now.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-19 16:35:48 +02:00
Mikko Perttunen
dcbc5e448b arm64: tegra: Add #power-domain-cells for BPMP
Add #power-domain-cells for the BPMP node on Tegra186 so that the power
domain provider may be used.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-19 16:35:48 +02:00
Mikko Perttunen
7b7ef49460 arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-13 15:07:44 +02:00
Alexandre Courbot
dfd7a3845a arm64: tegra: Add GPU node for Tegra186
Add the DT node for the GP10B GPU on Tegra186.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04 17:15:05 +02:00
Thierry Reding
0caafbde07 arm64: tegra: Add ethernet support for Tegra186
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data
transfer rates.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08 13:31:33 +01:00
Thierry Reding
73bf90d4d4 arm64: tegra: Add PMC controller on Tegra186
The NVIDIA Tegra186 SoC has a Power Management Controller that performs
various tasks related to system power, boot as well as suspend/resume.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08 13:31:31 +01:00
Thierry Reding
7bcf266462 arm64: tegra: Use symbolic reset identifiers
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-27 10:13:24 +01:00
Thierry Reding
c58f5f8848 arm64: tegra: Use symbolic clock identifiers
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25 09:23:56 +01:00
Thierry Reding
5edcebb96b arm64: tegra: Use symbolic HSP identifiers
Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25 09:23:55 +01:00
Thierry Reding
fc4bb754c8 arm64: tegra: Add GPIO controllers on Tegra186
Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21 10:43:40 +01:00
Thierry Reding
99425dfd6b arm64: tegra: Add SDHCI controllers on Tegra186
Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21 10:43:39 +01:00
Thierry Reding
40cc83b34c arm64: tegra: Add I2C controllers on Tegra186
Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21 10:43:39 +01:00
Thierry Reding
a7a77e2e83 arm64: tegra: Add serial ports on Tegra186
The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21 10:43:38 +01:00
Thierry Reding
cd6fe32e34 arm64: tegra: Add CPU nodes for Tegra186
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21 10:43:37 +01:00
Joseph Lo
39cb62cb89 arm64: tegra: Add Tegra186 support
This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
[treding@nvidia.com: remove leading 0 from unit-addresses]
[treding@nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21 10:43:36 +01:00