Stephen Boyd
2ed3b9103a
Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next
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- Qualcomm QCS404 CDSP clk support
- Qualcomm QCS404 Turing clk support
- Mediatek MT8183 clock support
- Mediatek MT8516 clock support
- Milbeaut M10V clk controller support
* clk-renesas:
clk: renesas: rcar-gen3: Remove unused variable
clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
clk: renesas: rcar-gen3: Rename DRIF clocks
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
clk: renesas: r8a774c0: Add Z2 clock
clk: renesas: r8a77990: Add Z2 clock
clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
math64: New DIV64_U64_ROUND_CLOSEST helper
clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
clk: renesas: r9a06g032: Add missing PCI USB clock
clk: renesas: r7s9210: Always use readl()
clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
* clk-qcom:
clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
clk: qcom: Add QCS404 TuringCC
clk: qcom: branch: Add AON clock ops
dt-bindings: clock: Introduce Qualcomm Turing Clock controller
clk: qcom: gcc-qcs404: Add CDSP related clocks and resets
* clk-mtk:
clk: mediatek: add clock driver for MT8516
dt-bindings: mediatek: apmixedsys: add support for MT8516
dt-bindings: mediatek: infracfg: add support for MT8516
dt-bindings: mediatek: topckgen: add support for MT8516
clk: mediatek: Allow changing PLL rate when it is off
clk: mediatek: Add MT8183 clock support
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
clk: mediatek: Add dt-bindings for MT8183 clocks
dt-bindings: ARM: Mediatek: Document bindings for MT8183
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
clk: mediatek: Add new clkmux register API
clk: mediatek: Disable tuner_en before change PLL rate
* clk-milbeaut:
clock: milbeaut: Add Milbeaut M10V clock controller
dt-bindings: clock: milbeaut: add Milbeaut clock description
* clk-imx:
clk: imx: correct pfdv2 gate_bit/vld_bit operations
clk: imx: clk-pllv3: mark expected switch fall-throughs
clk: imx8mq: Add dsi_ipg_div
clk: imx: pllv4: add fractional-N pll support
clk: imx: keep uart clock on during system boot
clk: imx: correct i.MX7D AV PLL num/denom offset
clk: imx6sll: Fix mispelling uart4_serial as serail
clk: imx: pll14xx: drop unused variable
clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
clk: imx5: Fix i.MX50 ESDHC clock registers
clk: imx5: Fix i.MX50 mainbus clock registers
clk: imx: Remove unused imx_get_clk_hw_fixed
dt-bindings: clock: imx7ulp: remove SNVS clock
clk: imx7ulp: remove snvs clock
2019-05-07 11:44:21 -07:00
Peng Fan
a3c9e13ff0
clk: imx: pll14xx: drop unused variable
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It does not make sense to only get value from pll->base and assign
to a local variable when recalc_rate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25 14:42:02 -07:00
Leonard Crestez
f89b9e1be7
clk: imx: Fix PLL_1416X not rounding rates
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Code which initializes the "clk_init_data.ops" checks pll->rate_table
before that field is ever assigned to so it always picks
"clk_pll1416x_min_ops".
This breaks dynamic rate rounding for features such as cpufreq.
Fix by checking pll_clk->rate_table instead, here pll_clk refers to
the constant initialization data coming from per-soc clk driver.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Fixes: 8646d4dcc7
2019-04-12 14:21:43 -07:00
Bai Ping
8646d4dcc7
clk: imx: Add PLLs driver for imx8mm soc
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New PLLs are introduced on i.MX8M Mini SOC.
PLL1416X is Integer PLL, PLL1443X is a Frac PLL.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
