3 Commits

Author	SHA1	Message	Date
Lars-Peter Clausen	62d1e7823d	clk: axi-clkgen: Add multi-parent support ... The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2016-01-29 17:06:14 -08:00
Lars-Peter Clausen	1887c3a64f	clk: axi-clkgen: Add support for v2 ... This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-02-26 17:02:29 -08:00
Lars-Peter Clausen	0e646c52cf	clk: Add axi-clkgen driver ... This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>	2013-03-19 17:20:30 -07:00