Child of mvpp2 ethernet do not have a reg property so the unit name
should not contain an address: remove them.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
As it was previously done for kirkwood and for aramda 370/XP, this adds
missing node labels to Armada 375 and SoC specific nodes to allow to
reference them more easily.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The actual frequency was updated in commit ae142bd997 ("ARM: mvebu:
Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
comment was not updated. Update it now.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Armada 375 has the same SATA IP as Armada 370 and Armada XP, which
requires the PHY speed to be set in the LP_PHY_CTL register for SATA
hotplug to work.
Therefore, this commit updates the compatible string used to describe
the SATA IP in Armada 375 from marvell,orion-sata to
marvell,armada-370-sata.
Fixes: 4de5908509 ("ARM: mvebu: add Device Tree description of the Armada 375 SoC")
Cc: <stable@vger.kernel.org>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add crypto related nodes in armada-375.dtsi.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
In order to optimize the L2 cache performance, this commit adjusts the
configuration of the L2 on the Cortex-A9 based Marvell EBU processors
(Armada 375, 38x and 39x), using the appropriate DT properties.
We enable double linefill, incr double linefill, data prefetch and
disable double linefill on wrap. This matches the configuration that
was fine tuned in the Marvell BSP.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJVa7zvAAoJEHm+PkMAQRiGtfMIAILs3sxFtrC1hApgcfRLF/7z
K34bwTRqErzqUO/orTwakEr9kSIpIL0zIPSryTCOTPZLfMGkQjhHXO3KR/DSbbTV
MZ8y/BM/yelFA/Np+1LjbiYjTNRnTRvCoaQihkIH8Rn02g7ob9HyL4gIGKpuGFcZ
04GacL2cgChqsRSACdNef948jCoJXKgcuDpe39DXphDWZnBKNZ3HFuJ6bryGJf9A
1/eCI4is85BNwKPemQUYR0xx83UIzDfrghatZP2mOCDDSA2MNg8HNxLTd12LGoQD
tfgX4B7aftzW9Y7GSEDfZ0IKm2NRzgPmCVj6PjVR/iI0lIK4Aq0Z/lDJxxEq3XQ=
=AJM5
-----END PGP SIGNATURE-----
Merge tag 'v4.1-rc6' into next/dt
Linux 4.1-rc6
Conflicts:
arch/arm/boot/dts/zynq-7000.dtsi
Resolution summary:
Mainline had an earlier version of the commit, resolve in favor of the
newer patch in next/dt branch.
Use the new compatible introduced in order to benefit of a wider and
more accurate range of baud rates to be used.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Whereas for Armada 370 and XP the main PLL frequency was 2GHz for the
Armada 375, 38x and 39x, the frequency is 1GHz. When writing support
for these last SoCs, there was no official value for the PLL. Now that
we have it, this patch fixes it in the device tree.
This value is currently only used by the NAND driver for the setting
the NAND timing. Fortunately it is not actually used: all the mainline
board with a NAND flash comes with a NAND device tree node using the
"marvell,nand-keep-config" property. With this property the timings
are not modified in the kernel driver and are kept from the
bootloader.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Marcin Wojtas <mw@semihalf.com>
The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available
to be used. This commit enables it in the devicetree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The Device Tree nodes describing the MPIC nodes on Armada 370, 375,
38x and XP had a unit address that did not match the first reg
property, as suggested by the ePAPR. This commit fixes that.
[gregory.clement@free-electrons.com: removed the armada-38x part, as it
was already applied by a previous patch]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds 'serialX' aliases for the various serial ports on
Armada 370, 375, 38x and XP platforms. It will allow the usage of the
stdout-path property.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Having aliases for Ethernet devices is useless, since the networking
subsystem unfortunately doesn't care about aliases to name network
interfaces.
Note that the 'aliases' nodes in armada-370-xp.dtsi and armada-xp.dtsi
become empty, but that we keep it as is since a followup patch will
re-add some aliases to it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds the standard uart0 and uart1 DT labels to the Device
Tree description of the Marvell Armada 375 SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The current GPL only licensing on the device tree makes it very
impractical for other software components licensed under another
license.
In order to make it easier for them to reuse our device trees,
relicense our device trees under a GPL/X11 dual-license.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Due to the special handling of window 13 on Armada 375 and Armada 38x
(similar to Armada XP), the MBus hardware block is *not* compatible
with the one used on Armada 370. Using the Armada 370 compatible
string on Armada 375 and 38x will lead to a non-working device if
window 13 ends up being used.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
On Armada 375, the USB cluster allows to control the cluster composed
of the USB2 and USB3 host controllers.
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415879269-29711-6-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that the timer and watchdog drivers support the Armada 375 usage of
the reference clock, we can enable it in the devicetree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414248522-16055-5-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375 SoC has the same real time clock as the one used in
other Marvell EBU platforms. This patch consequently updates the
Device Tree of the Armada 375 SoC to describe the internal RTC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1406817122-15675-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In Armada 375 SoCs, the MDIO is handled by a separate orion-mdio driver,
despite the register is contained within the "LMS" block of the network
controller.
Therefore we need to add the clock to the MDIO devicetree to prevent the
controller from being accesed with its clock gated. This is needed, for
instance, to be able to load the MDIO driver before the network driver.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1405961296-5846-7-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 375 SoCs contains two EHCI controllers. This commit
adds the Device Tree description of these interfaces at the SoC level,
and also enables the USB2 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-18-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 375 SoCs contain a xHCI controller. This commit
adds the Device Tree description of this interfaces at the SoC level,
and also enables the USB3 port on the Armada 375 DB platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-17-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Back when the Armada 370 and Armada XP initial support was introduced,
the only way to pass the clock frequency to the of_serial driver was
through a clock-frequency Device Tree property.
Thanks to 0bbeb3c3e8 ('of serial port
driver - add clk_get_rate() support'), it is possible to use the
standard 'clocks' DT property to reference the clock used for a
particular UART controller. This clock is then used by the of_serial
driver to retrieve the clock rate.
This commit modifies the SoC-level Device Tree files of Armada 370,
Armada XP, Armada 375 and Armada 38x to use this possibility. Since
there is no gatable clock for the UART controllers, we simply
reference the TCLK, which is the main SoC clock for the peripherals.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397806908-7550-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Instead of hardcoding the values of the interrupt flags, use the
macros provided by <include/dt-bindings/interrupt-controller/irq.h>
and <include/dt-bindings/interrupt-controller/arm-gic.h> for the
Armada 375 and Armada 38x Device Tree files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts,
use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to
clarify the Device Tree code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Some of the Armada 375/38x DTs that were recently submitted were still
using the old-style /include/ instead of the new-style, C-preprocessor
based #include. Since we are going to start including more headers,
switching to the C-preprocessor based includes is important.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375 SoC is a new SoC from Marvell, based on a dual core
Cortex-A9 and a number of hardware blocks that are common with earlier
SoCs from the mvebu family.
The provided Device Tree describes the following parts of the SoC:
* CPUs
* Device Bus
* Clocks
* Interrupt controllers: GIC and MPIC
* GPIO controllers
* I2C buses
* L2 cache
* MBus controller
* SDIO
* Pinctrl
* SATA
* Serial
* SPI buses
* System controller (for reboot)
* Timer
* XOR engines
* PCIe controllers
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
