Commit Graph

18 Commits

Author SHA1 Message Date
Nagarjuna Kristam
0a728e0bda soc/tegra: fuse: Add FUSE clock check in tegra_fuse_readl()
tegra_fuse_readl() can be called from drivers at any time. If this API
is called before tegra_fuse_probe(), we end up enabling the clock before
it is registered. Add a check for the FUSE clock in tegra_fuse_readl()
and propagate any errors.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-01 17:02:17 +02:00
Olof Johansson
761d3d22fb soc: tegra: Changes for v5.3-rc1
This contains a set of minor fixes and cleanups for core Tegra drivers.
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Merge tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc: tegra: Changes for v5.3-rc1

This contains a set of minor fixes and cleanups for core Tegra drivers.

* tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: Select pinctrl for Tegra194
  soc/tegra: fuse: Do not log error message on deferred probe
  soc/tegra: pmc: Add comments clarifying wake events
  soc/tegra: pmc: Avoid crash for non-wake IRQs
  soc/tegra: pmc: Fail to allocate more than one wake IRQ

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 05:42:42 -07:00
Thierry Reding
f0b2835f05 soc/tegra: fuse: Do not log error message on deferred probe
Recent changes have made it much more probable that clocks are not
available yet when the FUSE driver is first probed. However, that is a
situation that the driver can cope with just fine.

To avoid confusion, don't output an error when this happens.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-05 09:54:13 +02:00
Thomas Gleixner
9952f6918d treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:29:52 -07:00
Timo Alho
51294bf6b9 soc/tegra: fuse: Fix illegal free of IO base address
On cases where device tree entries for fuse and clock provider are in
different order, fuse driver needs to defer probing. This leads to
freeing incorrect IO base address as the fuse->base variable gets
overwritten once during first probe invocation. This leads to the
following spew during boot:

[    3.082285] Trying to vfree() nonexistent vm area (00000000cfe8fd94)
[    3.082308] WARNING: CPU: 5 PID: 126 at /hdd/l4t/kernel/stable/mm/vmalloc.c:1511 __vunmap+0xcc/0xd8
[    3.082318] Modules linked in:
[    3.082330] CPU: 5 PID: 126 Comm: kworker/5:1 Tainted: G S                4.19.7-tegra-gce119d3 #1
[    3.082340] Hardware name: quill (DT)
[    3.082353] Workqueue: events deferred_probe_work_func
[    3.082364] pstate: 40000005 (nZcv daif -PAN -UAO)
[    3.082372] pc : __vunmap+0xcc/0xd8
[    3.082379] lr : __vunmap+0xcc/0xd8
[    3.082385] sp : ffff00000a1d3b60
[    3.082391] x29: ffff00000a1d3b60 x28: 0000000000000000
[    3.082402] x27: 0000000000000000 x26: ffff000008e8b610
[    3.082413] x25: 0000000000000000 x24: 0000000000000009
[    3.082423] x23: ffff000009221a90 x22: ffff000009f6d000
[    3.082432] x21: 0000000000000000 x20: 0000000000000000
[    3.082442] x19: ffff000009f6d000 x18: ffffffffffffffff
[    3.082452] x17: 0000000000000000 x16: 0000000000000000
[    3.082462] x15: ffff0000091396c8 x14: 0720072007200720
[    3.082471] x13: 0720072007200720 x12: 0720072907340739
[    3.082481] x11: 0764076607380765 x10: 0766076307300730
[    3.082491] x9 : 0730073007300730 x8 : 0730073007280720
[    3.082501] x7 : 0761076507720761 x6 : 0000000000000102
[    3.082510] x5 : 0000000000000000 x4 : 0000000000000000
[    3.082519] x3 : ffffffffffffffff x2 : ffff000009150ff8
[    3.082528] x1 : 3d95b1429fff5200 x0 : 0000000000000000
[    3.082538] Call trace:
[    3.082545]  __vunmap+0xcc/0xd8
[    3.082552]  vunmap+0x24/0x30
[    3.082561]  __iounmap+0x2c/0x38
[    3.082569]  tegra_fuse_probe+0xc8/0x118
[    3.082577]  platform_drv_probe+0x50/0xa0
[    3.082585]  really_probe+0x1b0/0x288
[    3.082593]  driver_probe_device+0x58/0x100
[    3.082601]  __device_attach_driver+0x98/0xf0
[    3.082609]  bus_for_each_drv+0x64/0xc8
[    3.082616]  __device_attach+0xd8/0x130
[    3.082624]  device_initial_probe+0x10/0x18
[    3.082631]  bus_probe_device+0x90/0x98
[    3.082638]  deferred_probe_work_func+0x74/0xb0
[    3.082649]  process_one_work+0x1e0/0x318
[    3.082656]  worker_thread+0x228/0x450
[    3.082664]  kthread+0x128/0x130
[    3.082672]  ret_from_fork+0x10/0x18
[    3.082678] ---[ end trace 0810fe6ba772c1c7 ]---

Fix this by retaining the value of fuse->base until driver has
successfully probed.

Signed-off-by: Timo Alho <talho@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25 12:32:25 +01:00
Dmitry Osipenko
55a042b3f6 soc/tegra: fuse: Fix reading registers using DMA on Tegra20
FUSE driver doesn't configure DMA channel properly, because of it DMA
transfer is never issued and tegra20_fuse_read() always return 0x0.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 17:03:49 +01:00
Timo Alho
83468fe259 soc/tegra: fuse: Add Tegra186 support
Tegra210 and Tegra186 are mostly compatible from a fuses point of view.
However, speedo support is implemented in the BPMP firmware, hence the
implementation needs to be skipped in the fuses driver.

Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
[treding@nvidia.com: reword commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 12:43:29 +01:00
Thierry Reding
9261b43e70 soc/tegra: fuse: Add missing semi-colon
Commit 8a46828e623c ("soc/tegra: Register SoC device") added a new
initcall, but forgot to terminate the line with a semi-colon. Some
recent versions of GCC seem to report this as an error.

Fixes: 8a46828e623c ("soc/tegra: Register SoC device")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-08-23 11:54:27 +02:00
Thierry Reding
226cff485c soc/tegra: Restrict SoC device registration to Tegra
Commit 8a46828e623c ("soc/tegra: Register SoC device") added an initcall
to register the SoC device on Tegra. However, that code is unrestricted
and will run on all platforms, causing unwanted warnings.

Fix this by first checking that we're running on hardware that supports
the fuses block that we use to provide SoC information.

Fixes: 8a46828e623c ("soc/tegra: Register SoC device")
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Tested-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-08-23 11:54:10 +02:00
Thierry Reding
27a0342ac1 soc/tegra: Register SoC device
Move this code from arch/arm/mach-tegra and make it common among 32-bit
and 64-bit Tegra SoCs. This is slightly complicated by the fact that on
32-bit Tegra, the SoC device is used as the parent for all devices that
are instantiated from device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 16:43:13 +02:00
Paul Gortmaker
1859217bec soc: tegra: make fuse-tegra explicitly non-modular
The Makefiles currently controlling compilation of this code is:

drivers/soc/tegra/Makefile:obj-y += fuse/
drivers/soc/tegra/fuse/Makefile:obj-y += fuse-tegra.o

...meaning that it currently is not being built as a module by anyone.

Lets remove the couple traces of modularity so that when reading the
driver there is no doubt it is builtin-only.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04 15:43:52 +02:00
Thierry Reding
03b3f4c8b7 soc/tegra: fuse: Rename core_* to soc_*
There's a mixture of core_* and soc_* prefixes for variables storing
information related to the VDD_CORE rail. Choose one (soc_*) and use it
more consistently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16 10:38:29 +02:00
Thierry Reding
0dc5a0d836 soc/tegra: fuse: Add Tegra210 support
Add Tegra210 support to the fuses driver and add Tegra210-specific
speedo definitions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16 10:38:29 +02:00
Thierry Reding
7e939de1b2 soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers
Unifying the drivers makes it easier to restrict the legacy probing
paths to 32-bit ARM. This in turn will come in handy as support for
new 64-bit ARM SoCs is added.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16 10:38:28 +02:00
Thierry Reding
9b07eb0537 soc/tegra: fuse: Add Tegra132 support
Tegra132 is very similar to Tegra124 from a peripheral point of view and
uses the same fuse controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-09 16:14:36 +01:00
Vince Hsu
f9fc36618b soc/tegra: fuse: export tegra_sku_info
Some Tegra drivers might be compiled as kernel modules, and they need the
fuse information for initialization. One example is the GK20A Nouveau
driver. It needs the GPU speedo value to calculate frequency-voltage
table. So export the tegra_sku_info.

Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-12-02 15:43:37 +10:00
Thierry Reding
24fa5af810 soc/tegra: fuse: Set up in early initcall
Rather than rely on explicit initialization order called from SoC setup
code, use a plain initcall and rely on initcall ordering to take care of
dependencies.

This driver exposes some functionality (querying the chip ID) needed at
very early stages of the boot process. An early initcall is good enough
provided that some of the dependencies are deferred to later stages. To
make sure any abuses are easily caught, output a warning message if the
chip ID is queried while it can't be read yet.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 14:58:42 +02:00
Peter De Schrijver
783c8f4c84 soc/tegra: Add efuse driver for Tegra
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.

While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 14:36:01 +02:00