The statement
static const char *name[];
defines a modifiable array of pointers to constant chars. That is
*name[0] = 'f';
is forbidden, but
name[0] = "f";
is not. So marking an array that is defined as above with __initconst is
wrong. Either an additional const must be added such that the whole
definition reads:
static const char *const name[] __initconst;
or where this is not possible __initdata must be used.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
__initdata updated to __initconst for
static const struct of_device_id ti_clkdm_match_table[]
Signed-off-by: Fabian Frederick <fabf@skynet.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Since we have a fractional divider for the synthesizer, just implement
a simple multiply logic for the PLL.
It seems the PLL divider needs to have also the multiplier set for the PLL
to lock. At least I have not yet figured out if divided rates are doable.
So let's just ignore the PLL divider for now as the synthesizer has both
integer and fractional dividers so we don't even need to use the PLL
divider for the rates we know work with PLL locking.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.
Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
We need to round the calculated value to have it match the requested rate.
While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we
will need it in later patches for set_rate.
And let's remove two unused includes.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The OMAP DMTimer API, omap_dm_timer_set_source(), uses the clock name
timer_sys_ck for setting a timer's clock source for the source index
OMAP_TIMER_SRC_SYS_CLK. There is currently no clock alias data for
the Timers 13 through 16 for this clock name, so add the same.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent
of a timer node using 3 different values that use fixed parent names
for the clocks. The parent name, timer_sys_ck, is used for setting the
parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This
should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct
the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock
input.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The DT clock aliases for Timers use the legacy (non-DT) device
names and a source clock named sys_ck. OMAP5 is DT-boot only,
so correct the DT clock aliases to use the DT device names
instead. Also, the source clock name is corrected from 'sys_ck'
to 'timer_sys_ck', the name used by the OMAP dmtimer driver.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The DT clock aliases for timers using the legacy OMAP timer
device names have been cleaned up. These device names reflect
the names used in legacy boot, and are no longer applicable
as OMAP4 is DT boot only now.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2).
Add missing mcbsp clock aliases.
Collect the McBSP clock definition in one location at the same time.
Fixes the following warning on boot:
[ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16
[ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3)
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
In DT boot we do not have devices named as omap-mcbsp.X.
Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2).
Collect the McBSP clock definition in one location at the same time.
Fixes the following warning on boot:
[ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16
[ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3)
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is a case where NULL can be a valid return value for
ti_clk_get_reg_addr, specifically the case where both the provider index
and register offsets are zero. In this case, the current error checking
against a NULL pointer will fail. Thus, change the API to return a
ERR_PTR value in an error case, and change all the users of this API to
check against IS_ERR instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Commit 163152cbbe ("clk: ti: Add support for FAPLL on dm816x")
added basic support for the FAPLL on dm818x, but has a bug for the
parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3)
but the code is doing a shift on it.
This means the parent PLL won't get disabled even if all it's child
synthesizers are disabled.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
The 'ARM: OMAP3: legacy clock data move under clk driver' patch series
causes build errors when CONFIG_OMAP3 is not set:
drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll':
drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function)
const struct clk_ops *ops = &omap3_dpll_ck_ops;
^
drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function)
ops = &omap3_dpll_per_ck_ops;
^
drivers/built-in.o: In function `ti_clk_register_gate':
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait'
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait'
-in.o: In function `ti_clk_register_interface':
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_am35xx_ipss_wait'
drivers/built-in.o: In function `ti_clk_register_composite':
:(.text+0x3da768): undefined reference to `ti_clk_build_component_gate'
In order to fix that problem, this patch makes the omap3 legacy code
compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Introduces omap3 legacy clock data under clock driver. The clock data
is also in new format, which makes it possible to get rid of the
clk-private.h header. This patch also introduces SoC specific init
functions that shall be called from the low level init.
The data format used in this file has two possible evolution paths;
it can either be removed completely once no longer needed, or it will
be possible to retain the format and modify the TI clock driver to be
a loadable module at some point. The actual path to be followed
will be decided later.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this. The interface clock descriptor
itself is overloading the gate clock descriptor, thus it needs to
be called from the gate setup.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialialized slightly differently compared to
DT clocks, thus add support for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Legacy clock data for OMAP3 is being moved under clock driver, thus
base support for this is needed. This patch adds basic definitions for
clock init descriptors and core infrastructure for initialization,
which will be called from the OMAP3 clock init.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).
Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.
Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.
There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.
I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:
1. Setting the PLL to bypass mode also sets the child synthesizers
into bypass mode. As the bypass rate can also be generated by
the PLL in regular mode, there's no way for the child synthesizers
to detect the bypass mode based on the parent clock rate.
2. The PLL registers control the power for each of the child
syntheriser.
Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.
I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.
This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:
http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
It is safe to call the pm sync calls in interrupt context in this driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
As written, the __init for ti_clk_get_div_table is in the middle of the return
type.
The gcc documentation indicates that section attributes should be added to the
end of the function declaration:
extern void foobar (void) __attribute__ ((section ("bar")));
However gcc seems to be very permissive with where attributes can be placed.
clang on the other hand isn't so permissive, and fails if you put the section
definition in the middle of the return type:
drivers/clk/ti/divider.c:298:28: error: expected ';' after struct
static struct clk_div_table
^
;
drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this
declaration [-Wmissing-declarations]
static struct clk_div_table
^
drivers/clk/ti/divider.c:299:9: error: type specifier missing,
defaults to 'int' [-Werror,-Wimplicit-int]
__init *ti_clk_get_div_table(struct device_node *node)
~~~~~~ ^
drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types
returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types]
return table;
^~~~~
drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types
assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types]
*table = ti_clk_get_div_table(node);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~
3 warnings and 2 errors generated.
By convention, most of the kernel code puts section attributes between the
return type and function name. In the case where the return type is a pointer,
it's important to place the '*' on left of the __init.
This updated code works for both gcc and clang.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
I "forgot" to update the dtb and the kernel crashed:
|Unable to handle kernel NULL pointer dereference at virtual address 0000002e
|PC is at __clk_get_flags+0x4/0xc
|LR is at ti_dt_clockdomains_setup+0x70/0xe8
because I did not have the clock nodes. of_clk_get() returns an error
pointer which is not checked here.
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
of_clk_add_provider makes an internal copy of the parent_names property
while its called, thus it is no longer needed after this call and can
be freed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Previously, the TI clock driver initialized all the clocks hierarchically
under each separate clock provider node. Now, each clock that requires
IO access will instead check their parent node to find out which IO range
to use.
This patch allows the TI clock driver to use a few new features provided
by the generic of_clk_init, and also allows registration of clock nodes
outside the clock hierarchy (for example, any external clocks.)
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Stefan Assmann <sassmann@kpanic.de>
Acked-by: Tony Lindgren <tony@atomide.com>
There is no need to init .owner field.
Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"
This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Check for valid parameters in check rate. Else, we end up getting
errors.
This occurs as part of the inital clock tree update of child clock
nodes where new_rate could be 0 for non functional clocks.
Fixes: 9ac33b0ce8 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Check for valid parameters in check rate. Else, we end up getting errors
like:
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[ 0.000000] [<c0015160>] (unwind_backtrace) from [<c0011978>] (show_stack+0x10/0x14)
[ 0.000000] [<c0011978>] (show_stack) from [<c055f5f4>] (dump_stack+0x78/0x94)
[ 0.000000] [<c055f5f4>] (dump_stack) from [<c02e17cc>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02e17cc>] (Ldiv0) from [<c047d228>] (ti_clk_divider_set_rate+0x14/0x14c)
[ 0.000000] [<c047d228>] (ti_clk_divider_set_rate) from [<c047a938>] (clk_change_rate+0x138/0x180)
[ 0.000000] [<c047a938>] (clk_change_rate) from [<c047a908>] (clk_change_rate+0x108/0x180)
This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.
Fixes: b4761198bf ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
drivers and fixes/enhancements to existing clock drivers. There are also
some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
* improvements to printks on errors
* flattening the previously hierarchal structure of per-clock entries
in debugfs
* allow per-clock debugfs entries that are specific to a particular
clock driver
* configure initial clock parent and/or initial clock rate from Device
Tree
* several feature enhancements to the composite clock type
* misc fixes
New clock drivers added include:
* TI Palmas PMIC
* Allwinner A23 SoC
* Qualcomm APQ8084 and IPQ8064 SoCs
* Rockchip rk3188, rk3066 and rk3288 SoCs
* STMicroelectronics STiH407 SoC
* Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK down"
power saving feature for their Exynos4 & Exynos5 SoCs.
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Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are
also some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
- improvements to printks on errors
- flattening the previously hierarchal structure of per-clock entries
in debugfs
- allow per-clock debugfs entries that are specific to a particular
clock driver
- configure initial clock parent and/or initial clock rate from
Device Tree
- several feature enhancements to the composite clock type
- misc fixes
New clock drivers added include:
- TI Palmas PMIC
- Allwinner A23 SoC
- Qualcomm APQ8084 and IPQ8064 SoCs
- Rockchip rk3188, rk3066 and rk3288 SoCs
- STMicroelectronics STiH407 SoC
- Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK
down" power saving feature for their Exynos4 & Exynos5 SoCs"
* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: Add missing of_clk_set_defaults export
clk: checking wrong variable in __set_clk_parents()
clk: Propagate any error return from debug_init()
clk: clps711x: Add DT bindings documentation
clk: Add CLPS711X clk driver
clk: st: Use round to closest divider flag
clk: st: Update frequency tables for fs660c32 and fs432c65
clk: st: STiH407: Support for clockgenA9
clk: st: STiH407: Support for clockgenD0/D2/D3
clk: st: STiH407: Support for clockgenC0
clk: st: Add quadfs reset handling
clk: st: Add polarity bit indication
clk: st: STiH407: Support for clockgenA0
clk: st: STiH407: Support for A9 MUX Clocks
clk: st: STiH407: Support for Flexgen Clocks
clk: st: Adds Flexgen clock binding
clk: st: Remove uncessary (void *) cast
clk: st: use static const for clkgen_pll_data tables
clk: st: use static const for stm_fs tables
clk: st: Update ST clock binding documentation
...
ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
CC: Mike Turquette <mturquette@linaro.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
When setting the rate of a clock, by default the clock framework will
change the parent of the clock to the most suitable one in
__clk_mux_determine_rate() (most suitable by looking at the clock rate).
This is a rather dangerous default, and causes problems on AM43x when
using display and ethernet. There are multiple ways to select the clock
muxes on AM43x, and some of those clock paths have the same source
clocks for display and ethernet. When changing the clock rate for the
display subsystem, the clock framework decides to change the display mux
from the dedicated display PLL to a shared PLL which is used by the
ethernet, and then changes the rate of the shared PLL, breaking the
ethernet.
As I don't think there ever is a case where we want the clock framework
to automatically change the parent clock of a clock mux, this patch sets
the CLK_SET_RATE_NO_REPARENT for all ti,mux-clocks.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add a returned error code in the MAX_APLL_WAIT_TRIES case. Remove the
updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet
reached, because r is already 0 at this point.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
There is a cut and paste bug here which will lead to memory corruption
because we don't allocate enough data.
Fixes: 4d008589e2 ('CLK: TI: APLL: add support for omap2 aplls')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
3.16. They are simply fixes and code refactoring for the OMAP clock
drivers. The sunxi clock driver changes include splitting out the one
mega-driver into several smaller pieces and adding support for the A31
SoC clocks.
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Merge tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux
Pull more clock framework updates from Mike Turquette:
"This contains the second half the of the clk changes for 3.16.
They are simply fixes and code refactoring for the OMAP clock drivers.
The sunxi clock driver changes include splitting out the one
mega-driver into several smaller pieces and adding support for the A31
SoC clocks"
* tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
clk: sunxi: document PRCM clock compatible strings
clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
clk: sun6i: Protect SDRAM gating bit
clk: sun6i: Protect CPU clock
clk: sunxi: Rework clock protection code
clk: sunxi: Move the GMAC clock to a file of its own
clk: sunxi: Move the 24M oscillator to a file of its own
clk: sunxi: Remove calls to clk_put
clk: sunxi: document new A31 USB clock compatible
clk: sunxi: Implement A31 USB clock
ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies
CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies
ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)
CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)
dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings
ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock
CLK: TI: gate: add composite interface clock to OMAP2 only build
ARM: OMAP2: clock: add DT boot support for cpufreq_ck
CLK: TI: OMAP2: add clock init support
...
Pull networking updates from David Miller:
1) Seccomp BPF filters can now be JIT'd, from Alexei Starovoitov.
2) Multiqueue support in xen-netback and xen-netfront, from Andrew J
Benniston.
3) Allow tweaking of aggregation settings in cdc_ncm driver, from Bjørn
Mork.
4) BPF now has a "random" opcode, from Chema Gonzalez.
5) Add more BPF documentation and improve test framework, from Daniel
Borkmann.
6) Support TCP fastopen over ipv6, from Daniel Lee.
7) Add software TSO helper functions and use them to support software
TSO in mvneta and mv643xx_eth drivers. From Ezequiel Garcia.
8) Support software TSO in fec driver too, from Nimrod Andy.
9) Add Broadcom SYSTEMPORT driver, from Florian Fainelli.
10) Handle broadcasts more gracefully over macvlan when there are large
numbers of interfaces configured, from Herbert Xu.
11) Allow more control over fwmark used for non-socket based responses,
from Lorenzo Colitti.
12) Do TCP congestion window limiting based upon measurements, from Neal
Cardwell.
13) Support busy polling in SCTP, from Neal Horman.
14) Allow RSS key to be configured via ethtool, from Venkata Duvvuru.
15) Bridge promisc mode handling improvements from Vlad Yasevich.
16) Don't use inetpeer entries to implement ID generation any more, it
performs poorly, from Eric Dumazet.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1522 commits)
rtnetlink: fix userspace API breakage for iproute2 < v3.9.0
tcp: fixing TLP's FIN recovery
net: fec: Add software TSO support
net: fec: Add Scatter/gather support
net: fec: Increase buffer descriptor entry number
net: fec: Factorize feature setting
net: fec: Enable IP header hardware checksum
net: fec: Factorize the .xmit transmit function
bridge: fix compile error when compiling without IPv6 support
bridge: fix smatch warning / potential null pointer dereference
via-rhine: fix full-duplex with autoneg disable
bnx2x: Enlarge the dorq threshold for VFs
bnx2x: Check for UNDI in uncommon branch
bnx2x: Fix 1G-baseT link
bnx2x: Fix link for KR with swapped polarity lane
sctp: Fix sk_ack_backlog wrap-around problem
net/core: Add VF link state control policy
net/fsl: xgmac_mdio is dependent on OF_MDIO
net/fsl: Make xgmac_mdio read error message useful
net_sched: drr: warn when qdisc is not work conserving
...
MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum
frequency it can be locked at. Duty Cycle Correction circuit is used
to recover a correct duty cycle for achieving higher frequencies
(hardware internally switches output to M3 output(CLKOUTHIF) from M2
output (CLKOUT)).
So provide support to setup required data to handle Duty cycle by
the setting up the minimum frequency for DPLL. 1.4GHz is common
for all these devices and is based on Technical Reference Manual
information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output
Clocks Parameters", and equivalent information from DRA75x, DRA72x
documentation(SPRUHP2E, SPRUHI2P).
Signed-off-by: Nishanth Menon <nm@ti.com>
[t-kristo@ti.com: updated for latest dpll init API call]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
