In user xip test, there is a cplb error when ROMKERNEL try to mount romfs
using 'mount -t romfs /dev/mtdblock2 /mnt', becasue the CPLB setting is not
correct.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Change ce pin to PE4 according to new adaptor board and re-define ppi for vs6624
to avoid gpio conflict.
Signed-off-by: Vivi Li <vivi.li@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Customize the SEC interrupt priority array in machine ints-priority.c.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Turn SEC related macro CONFIG_BF60x into SEC_GCTL.
Move machine specific GPIO_PINT macros to machine gpio header.
Split SEC init_arch_irq() and vec_to_irq() from old SIC.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Add capabilities in adv7183_inputs to indicate that S_STD is supported.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
PPI driver has changed blank units from clocks to pixels.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
save and restore pint sec CTL
save and restore pint registers
add pint suspend and resume when suspend to mem
Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Pass wake up source mask and wakeup source polarity to deepsleep and
hibernate.
Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Otherwise, the compiler may optimize assemble code into 8bit access instruction
when target register is 8 bit width.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Add add deepsleep for bf60x.
1. Call DMC init functions to enter and exit DDR self refresh mode.
2. Wait till CGU PLL is locked after wake up and exit DDR self refresh mode.
3. Make asessembly function enter_deepsleep comply with C funtion ABI in
order to call other C functions.
4. Switch kernel stack by register EX_SCRATCH_REG.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Extend chip select number supported by spi master as well
because we can accept SPISEL1-SPISEL7 and all GPIO.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Pull arch/tile updates from Chris Metcalf:
"These changes provide support for PCIe root complex and USB host mode
for tilegx's on-chip I/Os.
In addition, this pull provides the required underpinning for the
on-chip networking support that was pulled into 3.5. The changes have
all been through LKML (with several rounds for PCIe RC) and on
linux-next."
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
tile: updates to pci root complex from community feedback
bounce: allow use of bounce pool via config option
usb: add host support for the tilegx architecture
arch/tile: provide kernel support for the tilegx USB shim
tile pci: enable IOMMU to support DMA for legacy devices
arch/tile: enable ZONE_DMA for tilegx
tilegx pci: support I/O to arbitrarily-cached pages
tile: remove unused header
arch/tile: tilegx PCI root complex support
arch/tile: provide kernel support for the tilegx TRIO shim
arch/tile: break out the "csum a long" function to <asm/checksum.h>
arch/tile: provide kernel support for the tilegx mPIPE shim
arch/tile: common DMA code for the GXIO IORPC subsystem
arch/tile: support MMIO-based readb/writeb etc.
arch/tile: introduce GXIO IORPC framework for tilegx
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Merge tag 'please-pull-misc-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux
Pull misc Itanium fixes from Tony Luck.
* tag 'please-pull-misc-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux:
debug: Do not permit CONFIG_DEBUG_STACK_USAGE=y on IA64 or PARISC
[IA64] Port OOM changes to ia64_do_page_fault
- Migration off of old-style dynamic IRQ API.
- irqdomain and generic irq chip propagation.
- div4/6 clock consolidation, another step towards co-existing
with the common struct clk infrastructure.
- Extensive PFC rework
- Decoupling GPIO from pin state.
- Initial pinctrl support to facilitate incremental migration
off of legacy pinmux.
- gpiolib support made optional, and made pinctrl-backed.
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Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
Pull SuperH updates from Paul Mundt:
- Migration off of old-style dynamic IRQ API.
- irqdomain and generic irq chip propagation.
- div4/6 clock consolidation, another step towards co-existing with the
common struct clk infrastructure.
- Extensive PFC rework
- Decoupling GPIO from pin state.
- Initial pinctrl support to facilitate incremental migration off of
legacy pinmux.
- gpiolib support made optional, and made pinctrl-backed.
* tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (38 commits)
sh: pfc: pin config get/set support.
sh: pfc: Prefer DRV_NAME over KBUILD_MODNAME.
sh: pfc: pinctrl legacy group support.
sh: pfc: Ignore pinmux GPIOs with invalid enum IDs.
sh: pfc: Export pinctrl binding init symbol.
sh: pfc: Error out on pinctrl init resolution failure.
sh: pfc: Make pr_fmt consistent across pfc drivers.
sh: pfc: pinctrl legacy function support.
sh: pfc: Rudimentary pinctrl-backed GPIO support.
sh: pfc: Dumb GPIO stringification.
sh: pfc: Shuffle PFC support core.
sh: pfc: Verify pin type encoding size at build time.
sh: pfc: Kill off unused pinmux bias flags.
sh: pfc: Make gpio chip support optional where possible.
sh: pfc: Split out gpio chip support.
sh64: Fix up section mismatch warnings.
sh64: Attempt to make reserved insn trap handler resemble C.
sh: Consolidate die definitions for trap handlers.
sh64: Kill off old exception debugging helpers.
sh64: Use generic unaligned access control/counters.
...
