Now that the helpers provide the inbound resources in the host bridge
'dma_ranges' resource list, convert Broadcom iProc host bridge to use
the resource list to setup the inbound addresses.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Convert the iProc host bridge to use the common
pci_parse_request_of_pci_ranges().
There's no need to assign the resources to a temporary list, so just use
bridge->windows directly.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Fix typos in drivers/pci. Comment and whitespace changes only.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
The iProc host controller allows only a subset of physical address space as
target of inbound PCI memory transaction addresses.
PCI device memory transactions targeting memory regions that are not
allowed for inbound transactions in the host controller are rejected by the
host controller and cannot reach the upstream buses.
The firmware device tree description defines the DMA ranges that are
addressable by devices DMA transactions; parse the device tree dma-ranges
property and add its ranges to the PCI host bridge dma_ranges list; the
iova_reserve_pci_windows() call executed at iommu_dma_init_domain() will
reserve the IOVA address ranges that are not addressable (ie memory holes
in the dma-ranges set) so that they are not allocated to PCI devices for
DMA transfers.
All allowed address ranges are listed in the dma-ranges DT parameter. For
example:
dma-ranges = < \
0x43000000 0x00 0x80000000 0x00 0x80000000 0x00 0x80000000 \
0x43000000 0x08 0x00000000 0x08 0x00000000 0x08 0x00000000 \
0x43000000 0x80 0x00000000 0x80 0x00000000 0x40 0x00000000>
In the above example of dma-ranges, memory address from
0x0 - 0x80000000,
0x100000000 - 0x800000000,
0x1000000000 - 0x8000000000 and
0x10000000000 - 0xffffffffffffffff.
are not allowed to be used as inbound addresses.
Based-on-a-patch-by: Oza Pawandeep <oza.oza@broadcom.com>
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[bhelgaas: fix function prototype style]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
iProc config read flag has to be enabled for PAXBv2 instead of PAXB.
Fixes: f78e60a29d ("PCI: iproc: Reject unconfigured physical functions from PAXC")
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
The IProc host controller has I/O memory windows allocated in
the AXI memory map that can be used to address PCI I/O memory
space.
Mapping from AXI memory windows to PCI outbound memory windows is
carried out in the host controller through OARR/OMAP registers pairs
that permit to define power of two region size AXI<->PCI mappings, the
smallest of which is 128MB.
Current code enables AXI memory window to PCI outbound memory window
mapping only for AXI windows matching one of the OARR/OMAP window sizes,
that are SoC dependent and the smallest of which is 128MB.
Some SoCs implementing the IProc host controller have a 32-bit AXI
memory window into PCI I/O memory space, eg:
Base address | Size
-----------------------------
(1) 0x42000000 | 0x2000000
(2) 0x400000000 | 0x80000000
but its size (32MB - (1) above) is smaller than the smallest AXI<->PCI
region size provided by OARR (128MB), so the current driver rejects
mappings for the 32-bit region making the IProc host controller driver
unusable on 32-bit systems.
However, there is no reason why the 32-bit I/O memory window cannot be
enabled by mapping it through an OARR/OMAP region bigger in size (ie
32-bit AXI window size is 32MB but can be mapped using a 128MB OARR/OMAP
region).
Allow outbound window configuration of I/O memory windows that
are smaller in size than the host controller OARR/OMAP region, so
that the 32-bit AXI memory window can actually be enabled,
making the IProc host controller operational on 32-bit systems.
Link: https://lore.kernel.org/linux-pci/1551415936-30174-3-git-send-email-srinath.mannam@broadcom.com/
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
[lorenzo.pieralisi@arm.com: rewrote the commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
The IPROC PCIe host controller implementation returns CFG_RETRY_STATUS
(0xffff0001) data when it receives a CRS completion, regardless of the
address of the read or the CRS Software Visibility Enable bit. As a
workaround the driver retries in software any read that returns
CFG_RETRY_STATUS even though, for reads of registers that are not Vendor
ID, the register value can correspond to CFG_RETRY_STATUS; this
situation would cause a timeout and failure of reading a valid register
value.
IPROC PCIe host controller PAXB v2 has a register to show config read
status flags like SC, UR, CRS and CA. Using this status flag,
an extra check is added to confirm the CRS using status flags before
reissuing a config read, fixing the issue.
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
[lorenzo.pieralisi@arm.com: rewrote commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
The call to of_parse_phandle() returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
iproc_msi_init() also calls of_node_get() to increase refcount:
proc_msi_init()
-> iproc_msi_alloc_domains()
-> pci_msi_create_irq_domain()
-> msi_create_irq_domain()
-> irq_domain_create_linear()
-> __irq_domain_add()
so irq_domain will not be affected when it is released.
Detected by coccinelle with the following warnings:
./drivers/pci/controller/pcie-iproc.c:1323:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1299, but without a corresponding object release within this function.
./drivers/pci/controller/pcie-iproc.c:1330:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1299, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Fix previous incorrect logic that limits PAXC slot number to zero only.
In order for SRIOV/VF to work, we need to allow the slot number to be
greater than zero.
Fixes: 46560388c4 ("PCI: iproc: Allow multiple devices except on PAXC")
Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andy Gospodarek <gospo@broadcom.com>
Reduce inbound/outbound mapping print level from dev_info() to
dev_dbg(). This reduces the console logs during Linux boot process.
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
PAXC is an emulated PCIe root complex internally in various Broadcom
based SoCs. PAXC internally connects to the embedded network processor
within these SoCs, with the embedeed network processor exposed as an
endpoint device.
The number of physical functions from the embedded network processor
that can be accessed depends on the firmware configuration.
Unfortunately, due to an ASIC bug, unconfigured physical functions cannot
be properly hidden from the root complex during enumerattion. As a
result, config write access to these unconfigured physical functions
during enumeration will cause a bus lock up on the embedded network
processor.
Fortunately, these unconfigured physical functions contain a very
specific, staled PCIe device ID 0x168e. By making use of this device ID,
one is able to terminate the enumeration early in the vendor/device ID
config read.
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
The internal MSI parsing logic in certain revisions of PAXC root
complexes does not work properly and can cause corruptions on the
writes transactions so they need to be disabled.
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
On certain versions of Broadcom PAXC based root complexes, certain
regions of the configuration space are corrupted. As a result, it
prevents the Linux PCIe stack from traversing the linked list of the
capability registers completely and therefore the root complex is
not advertised as "PCIe capable". This prevents the correct PCIe RID
from being parsed in the kernel PCIe stack. A correct RID is required
for mapping to a stream ID from the SMMU or the device ID from the
GICv3 ITS.
This patch fixes up the issue by manually populating the related
PCIe capabilities.
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
Native PCI drivers for root complex devices were originally all in
drivers/pci/host/. Some of these devices can also be operated in endpoint
mode. Drivers for endpoint mode didn't seem to fit in the "host"
directory, so we put both the root complex and endpoint drivers in
per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc.
These per-device directories contain trivial Kconfig and Makefiles and
clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and
collect all the device-specific drivers there.
No functional change intended.
Link: https://lkml.kernel.org/r/1520304202-232891-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
