Commit Graph

527 Commits

Author SHA1 Message Date
Michel Alexandre Salim
070d329ae5 drm/i915: Add quirk to disable SSC on Sony Vaio Y2
Using the new quirk added to support disabling SSC on Lenovo U160
(#36656, commit 435793dfb8), also register
the Vaio as a special case and disable SSC for it.

This patch fixes #34437 on fdo bugzilla:
https://bugs.freedesktop.org/show_bug.cgi?id=34437

Signed-off-by: Michel Alexandre Salim <salimma@fedoraproject.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-29 15:13:53 -07:00
Jesse Barnes
013a41ec54 drm/i915: provide more error output when mode sets fail
If a mode set fails we may get a message from drm_crtc_helper if we're lucky,
but it won't tell us anything about *why* we failed to set a mode.  So
add a few DRM_ERRORs for the cases that shouldn't happen so we can debug
things more easily.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-29 15:09:06 -07:00
Jesse Barnes
cb0e093162 drm/i915: fix CB tuning check for ILK+
CB tuning is needed to handle potential process variations that might
cause clock jitter for certain PLL settings.  However, we were setting
it incorrectly since we were using the wrong M value as a check (M1 when
we needed to use the whole M value).  Fix it up, making my HDMI
attached display a little prettier (used to have occasional dots crawl
across the display).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-28 16:51:09 -07:00
Keith Packard
d74362c9e4 drm/i915: Flush other plane register writes
Writes to the plane control register are buffered in the chip until a
write to the DSPADDR (pre-965) or DSPSURF (post-965) register occurs.

This patch adds flushes in:

	intel_enable_plane
	gen6_init_clock_gating
	ivybridge_init_clock_gating

Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-28 16:28:35 -07:00
Jesse Barnes
2704cf5fbd drm/i915: flush plane control changes on ILK+ as well
After writing to the plane control reg we need to write to the surface
reg to trigger the double buffered register latch.  On previous
chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg
that triggers the double buffer latch.

v2: write DSPADDR too to cover pre-965 chipsets
v3: use flush_display_plane instead, that's what it's for
v4: send the right patch

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-28 16:28:31 -07:00
Jesse Barnes
3bcf603f6d drm/i915: apply timing generator bug workaround on CPT and PPT
On CougarPoint and PantherPoint PCH chips, the timing generator may fail
to start after DP training completes.  This is due to a bug in the
FDI autotraining detect logic (which will stall the timing generator and
re-enable it once training completes), so disable it to avoid silent DP
mode setting failures.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-28 16:28:21 -07:00
Keith Packard
120eced9ef drm/i915: Set crtc DPMS mode to ON in intel_crtc_mode_set
This corrects the DPMS mode tracking so that the DPMS code will
actually turn the CRTC off the next time the screen saves.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-28 16:27:39 -07:00
Keith Packard
f0575e9297 drm/i915: DP_PIPE_ENABLED must check transcoder on CPT
Display port pipe selection on CPT is not done with a bit in the
output register, rather it is controlled by a couple of bits in the
separate transcoder register which indicate which display port output
is connected to the transcoder.

This patch replaces the simplistic macro DP_PIPE_ENABLED with the
rather more complicated function dp_pipe_enabled which checks the
output register to see if that is enabled, and then goes on to either
check the output register pipe selection bit (on non-CPT) or the
transcoder DP selection bits (on CPT).

Before this patch, any time the mode of pipe A was changed, any
display port outputs on pipe B would get disabled as
intel_disable_pch_ports would ensure that the mode setting operation
could occur on pipe A without interference from other outputs
connected to that pch port

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
2011-07-28 15:47:22 -07:00
Jesse Barnes
9c54c0dd94 drm/i915: load the LUT before pipe enable on ILK+
Per the specs and to address
https://bugs.freedesktop.org/show_bug.cgi?id=36888.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@kernel.org
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-22 13:37:00 -07:00
Keith Packard
435793dfb8 drm/i915: Add quirk to disable SSC on Lenovo U160 LVDS
We've tried several times to make this machine 'just work', but every
patch that does causes many other machines to fail. This adds a quirk
which special cases this hardware and forces ssc to be
disabled. There's no way to override this from the command line; that
would be a significantly more invasive change.

This patch fixes #36656 on fdo bugzilla:
https://bugs.freedesktop.org/show_bug.cgi?id=36656

Signed-off-by: Keith Packard <keithp@keithp.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=36656
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13 23:53:41 -07:00
Jesse Barnes
7c9017e5b7 drm/i915: add Ivy Bridge page flip support
Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.

Fixes bugs:

	https://bugs.freedesktop.org/show_bug.cgi?id=38362
	https://bugs.freedesktop.org/show_bug.cgi?id=38392
	https://bugs.freedesktop.org/show_bug.cgi?id=38393

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by:  Jian J Zhao <jian.j.zhao@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-26 19:11:22 -07:00
Jesse Barnes
8c9f3aaf8e drm/i915: split page flip queueing into per-chipset functions
This makes things a little clearer and prevents us from running old code
on a new chipset that may not be supported.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewied-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-26 19:11:16 -07:00
Keith Packard
efc2924e73 drm/i915: Call intel_enable_plane from i9xx_crtc_mode_set (again)
This change got placed in the ironlake path instead of the 9xx path
during a recent code shuffle.

Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-21 10:57:05 -07:00
Chris Wilson
9f405100f2 drm/i915: Replace ironlake_compute_wm0 with g4x_compute_wm0
The computation of the first-level watermarks for g4x and gen5+ are
based on the same algorithm, so we can refactor those code paths to
use a single function.

Note that g4x_compute_wm0 takes a 'plane' argument while
ironlake_compute_wm0 took a 'pipe' argument. Both should have used a
'plane' argument, so this patch fixes that as well (not that it caused
a problem; ironlake always uses pipe == plane).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-04 10:40:59 -07:00
Jason Stubbs
95e0ee92d3 drm/i915: fix regression after clock gating init split
During the refactoring in revision 6067aaeadb,
the intel_enable_clock_gating was split up into several functions that are
then called indirectly. However, which function to call was not specified for
the IS_PINEVIEW() case. This patch specifies the correct gating function.

Signed-off-by: Jason Stubbs <jasonbstubbs@gmail.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-04 10:40:26 -07:00
Linus Torvalds
98b98d3163 Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (169 commits)
  drivers/gpu/drm/radeon/atom.c: fix warning
  drm/radeon/kms: bump kms version number
  drm/radeon/kms: properly set num banks for fusion asics
  drm/radeon/kms/atom: move dig phy init out of modesetting
  drm/radeon/kms/cayman: fix typo in register mask
  drm/radeon/kms: fix typo in spread spectrum code
  drm/radeon/kms: fix tile_config value reported to userspace on cayman.
  drm/radeon/kms: fix incorrect comparison in cayman setup code.
  drm/radeon/kms: add wait idle ioctl for eg->cayman
  drm/radeon/cayman: setup hdp to invalidate and flush when asked
  drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked
  agp/uninorth: Fix lockups with radeon KMS and >1x.
  drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only
  drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
  drm/radeon/kms: fixup eDP connector handling
  drm/radeon/kms: bail early for eDP in hotplug callback
  drm/radeon/kms: simplify hotplug handler logic
  drm/radeon/kms: rewrite DP handling
  drm/radeon/kms/atom: add support for setting DP panel mode
  drm/radeon/kms: atombios.h updates for DP panel mode
  ...
2011-05-24 12:06:40 -07:00
Dave Airlie
351fc4d660 Merge remote branch 'keithp/drm-intel-next' of ../drm-next into drm-core-next
* 'keithp/drm-intel-next' of ../drm-next:
  drm/i915: initialize gen6 rps work queue on Sandy Bridge and Ivy Bridge
  drm/i915/sdvo: Reorder i2c initialisation before ddc proxy
  drm/i915: FDI link training broken on Ironlake by Ivybridge integration
  drm/i915: enable rc6 by default
  drm/i915: add fbc enable flag, but disable by default
  drm/i915: clean up unused ring_get_irq/ring_put_irq functions
  drm/i915: fix user irq miss in BSD ring on g4x
2011-05-20 11:30:02 +10:00
Keith Packard
61e499bf05 drm/i915: FDI link training broken on Ironlake by Ivybridge integration
Commit 357555c00f split out IVB-specific
register definitions for FDI link training, but a piece of that commit
stopped executing some critical code on Ironlake systems while leaving
it running on Sandybridge.

Turn that code back on both Ironlake and Sandybridge

Signed-off-by: Keith Packard <keithp@keithp.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-05-17 16:20:54 -07:00
Jesse Barnes
c1a9f04763 drm/i915: add fbc enable flag, but disable by default
FBC has too many corner cases that we don't currently deal with, so
disable it by default so we can enable more important features like RC6,
which conflicts in some configurations.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31742
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-17 14:31:26 -07:00
Dave Airlie
69f7876b2a Merge remote branch 'keithp/drm-intel-next' of /ssd/git/drm-next into drm-core-next
* 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits)
  drm/i915: split PCH clock gating init
  drm/i915: add Ivybridge clock gating init function
  drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.
  drm/i915: Add support for fence registers on Ivybridge.
  drm/i915: Use existing function instead of open-coding fence reg clear.
  drm/i915: split clock gating init into per-chipset functions
  drm/i915: set IBX pch type explicitly
  drm/i915: add Ivy Bridge PCI IDs and driver feature structs
  drm/i915: add PantherPoint PCH ID
  agp/intel: add Ivy Bridge support
  drm/i915: ring support for Ivy Bridge
  drm/i915: page flip support for Ivy Bridge
  drm/i915: interrupt & vblank support for Ivy Bridge
  drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
  drm/i915: manual FDI training for Ivy Bridge
  drm/i915: add swizzle/tiling support for Ivy Bridge
  drm/i915: Ivy Bridge has split display and pipe control
  drm/i915: add IS_IVYBRIDGE macro for checks
  drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
  drm/i915: split enable/disable vblank code into chipset specific functions
  ...
2011-05-16 10:45:40 +10:00
Jesse Barnes
645c62a5e9 drm/i915: split PCH clock gating init
Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:53 -07:00
Jesse Barnes
28963a3eb5 drm/i915: add Ivybridge clock gating init function
Some of the bits have changed, including one we were setting that enables
a VGA test mode, preventing pipe B from working at all.  So add a new
IVB specific function with the right bits.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:53 -07:00
Jesse Barnes
6067aaeadb drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:50 -07:00
Jesse Barnes
51d56126a2 drm/i915: page flip support for Ivy Bridge
Treat Ivy Bridge like previous chips as far as flip submission is
concerned.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:10:13 -07:00
Jesse Barnes
fe100d4da1 drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
Not fully tested.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:08:31 -07:00
Jesse Barnes
357555c00f drm/i915: manual FDI training for Ivy Bridge
A0 stepping chips need to use manual training, but the bits have all
moved.  So fix things up so we can at least train FDI for VGA links.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:06:22 -07:00
Jesse Barnes
674cf96761 drm/i915: make FDI training a display function
Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:02:19 -07:00
Linus Torvalds
982b2035d9 Revert "drm/i915: Only enable the plane after setting the fb base (pre-ILK)"
This reverts commit 49183b2818.

Quoth Franz Melchior:

  "This patch introduces a bug on my infamous "Acer Travelmate
   5735Z-452G32Mnss": when KMS takes over, the frame buffer contents get
   completely garbled up on screen, with colored stripes and unreadable
   text (photo on request).  Only when X11 is started, the screen gets
   restored again.  Closing and re-opening the lid partly cures the
   mess, too: it makes the font readable, though horizontally stretched."

Acked-by: Keith Packard <keithp@keithp.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-05-12 12:19:43 -07:00
Ben Widawsky
4912d04193 drm/i915: move gen6 rps handling to workqueue
The render P-state handling code requires reading from a GT register.
This means that FORCEWAKE must be written to, a resource which is shared
and should be protected by struct_mutex. Hence we can not manipulate
that register from within the interrupt handling and so must delegate
the task to a workqueue.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:47 -07:00
Ben Widawsky
d1ebd816e6 drm/i915: forcewake struct mutex locking fixes
Found by the new strict checking for the mutex being held whilst
manipulating the forcewake status.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:47 -07:00
Ben Widawsky
fcca792629 drm/i915: reference counted forcewake
Provide a reference count to track the forcewake state of the GPU and
give a safe mechanism for userspace to wake the GT. This also potentially
saves a UC read if the GT is known to be awake already.

The reference count is atomic, but the register access and hardware wake
sequence is protected by struct_mutex.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:46 -07:00
Chris Wilson
2c7111dbae drm/i915: Disable all outputs early, before KMS takeover
If the outputs are active and continuing to access the GATT when we
teardown the PTEs, then there is a potential for us to hang the GPU.
The hang tends to be a PGTBL_ER with either an invalid host access or
an invalid display plane fetch.

v2: Reorder IRQ initialisation to defer until after GEM is setup.

Reported-by: Pekka Enberg <penberg@kernel.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> (855GM)
Tested-by: Pekka Enberg <penberg@kernel.org>
           # note that this doesn't fix the underlying problem of the
             PGTBL_ER and pipe underruns being reported immediately upon
             init on his 965GM MacBook
Reported-and-tested-by: Rick Bramley <richard.bramley@hp.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35635
Reported-and-tested-by: Zdenek Kabelac <zdenek.kabelac@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36048
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2011-05-10 13:56:44 -07:00
Jesse Barnes
7df8721beb drm/i915: use i915_enable_rc6 on SNB too
For debug & testing.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:42 -07:00
Ben Widawsky
4a246cfc3c drm/i915: fix rc6 initialization on Ironlake
There is a race condition between setting PWRCTXA and executing
MI_SET_CONTEXT. PWRCTXA must not be set until a valid context has been
written (or else the GPU could possible go into rc6, and return to an
invalid context).

Reported-and-Tested-by: Gu Rui <chaos.proton@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:41 -07:00
Ben Widawsky
2c34b850ee drm/i915: fix ilk rc6 teardown locking
In the failure cases during rc6 initialization, both the power context
and render context may get !refcount without holding struct_mutex.
However, on rc6 disabling, the lock is held by the caller.

Rearranged the locking so that it's safe in both cases.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:40 -07:00
Eric Anholt
273e27ca80 drm/i915: Fold the DPLL limit defines into the structs that use them.
They're used in one place, and not providing any descriptive value,
with their names just being approximately the conjunction of the
struct name and the struct field.

This diff was produced with gcc -E, copying the new struct definitions
out, moving a couple of the old comments into place in the new
structs, and reindenting.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:39 -07:00
Eric Anholt
fae14981ce drm/i915: Clean up leftover DPLL and LVDS register choice from pch split.
We used to have these from the product of (pch, non-pch) * (pipe a,
pipe b).  Now we can just use the nice per-pipe reg macros in the
split out crtc_mode_sets.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:38 -07:00
Eric Anholt
a07d678705 drm/i915: Drop remaining pre-Ironlake code from ironlake_crtc_mode_set().
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:37 -07:00
Eric Anholt
8febb2974f drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set().
Ironlake is where the PCH split started.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:37 -07:00
Eric Anholt
db244b60e7 drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set().
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:36 -07:00
Eric Anholt
c713bb087e drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set.
While g4x had DP, eDP came with Ironlake, so we don't need that code here.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:35 -07:00
Eric Anholt
929c77fb38 drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set().
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:29 -07:00
Eric Anholt
0b701d27b3 drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:54:50 -07:00
Eric Anholt
f564048e20 drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines.
This path, which shouldn't be *that* complicated, is now so littered
with per-chipset tweaks that it's hard to trace the order of what
happens.  HAS_PCH_SPLIT() is the most radical change across chipsets,
so it seems like a natural split to simplify the code.

This first commit just copies the existing code without changing
anything.

v2: updated to track removal of call to intel_enable_plane from i9xx_crtc_mode_set

Signed-off-by: Eric Anholt <eric@anholt.net>
Hella-acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:54:39 -07:00
Chris Wilson
d2dff872ac drm/i915: Attach a fb to the load-detect pipe
We need to ensure that we feed valid memory into the display plane
attached to the pipe when switching the pipe on. Otherwise, the display
engine may read through an invalid PTE and so throw an PGTBL_ER
exception.

As we need to perform load detection before even the first object is
allocated for the fbdev, there is no pre-existing object large enough
for us to borrow to use as the framebuffer. So we need to create one
and cleanup afterwards. At other times, the current fbcon may be large
enough for us to borrow it for duration of load detection.

Found by assert_fb_bound_for_plane().

Reported-by: Knut Petersen <Knut_Petersen@t-online.de>
References: https://bugs.freedesktop.org/show_bug.cgi?id=36246
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:18 -07:00
Chris Wilson
0622a53c60 drm/i915: Remove dead code from intel_release_load_detect_pipe()
As we now never attempt to steal a crtc for load detection, we either
set a mode on a new pipe, or change the dpms mode on an existing pipe.
Never both, so we can simplify the code slightly.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:17 -07:00
Chris Wilson
6492711d05 drm/i915: Remove dead code from intel_get_load_detect_pipe()
As we only allow the use of a disabled CRTC, we don't need to handle the
case where we are reusing an already enabled pipe.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:17 -07:00
Chris Wilson
4fbf69138a drm/i915: Pass the saved adjusted_mode when adding to the load-detect crtc
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:16 -07:00
Chris Wilson
7a5e4805bd drm/i915: Remove unused supported_crtc from intel_load_detect_pipe
... and the no longer relevant comment. The code ceased stealing a pipe
for load detection a long time ago.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:15 -07:00
Chris Wilson
8261b19173 drm/i915: Don't store temporary load-detect variables in the generic encoder
Keep all the state required for undoing and restoring the previous pipe
configuration together in a single struct passed from
intel_get_load_detect_pipe() to intel_release_load_detect_pipe() rather
than stuffing them inside the common encoder structure.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:15 -07:00