Commit Graph

3 Commits

Author SHA1 Message Date
Sharat Masetty
9fb4bfd0be drm/msm/a6xx: Send the right perf index value to GMU
The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-03 20:24:54 -04:00
Colin Ian King
546907de99 drm/msm: a6xx: fix spelling mistake: "initalization" -> "initialization"
Trivial fix to spelling mistake in dev_err message and comment

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-10 18:49:18 -04:00
Jordan Crouse
4b565ca5a2 drm/msm: Add A6XX device support
Add support for the A6XX family of Adreno GPUs. The biggest addition
is the GMU (Graphics Management Unit) which takes over most of the
power management of the GPU itself but in a ironic twist of fate
needs a goodly amount of management itself. Add support for the
A6XX core code, the GMU and the HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-10 18:49:18 -04:00