Commit Graph

10346 Commits

Author SHA1 Message Date
Hawking Zhang
068ed934ee drm/amdgpu/gfx10: new approach to load pfp fw (v4)
gfx10 allows to only upload pfp jumptable while save the whole
pfp image at gtt memory.

v2: program CP_PFP_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo
v4: split common code from gfx10 code

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:19:44 -05:00
Hawking Zhang
225cef9d88 drm/amdgpu: add nbio v2.3 for navi10 (v4)
nbio handles bus io functionality.

v1: add place holder and initial basic nbio v2.3 functions (Ray)
v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking)
v3: squash in updates (Alex)
v4: whitespace fix (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:18:36 -05:00
Leo Liu
b45ddfe811 drm/amdgpu: add nbio callbacks for vcn doorbell support
For Navi10 VCN2.0, the engine supports Doorbell

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
09fa0613bd drm/amdgpu: query vram_width from vram_info table
Driver will get channel_number and channel_width from
vram_info table, then calculate vram_width by multiply
channel_number by channel_width

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
89d7a79c7b drm/amdgpu: query vram type from atomfirmware vram_info
vram_type is saved in member vram_module[0].memory_type

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
98cd7f5b18 drm/amdgpu: add navi pm4 header
A pm4 header for Navi. PM4 is the packet format used
by the compute and gfx engines.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Hawking Zhang
9a87c32fda drm/amdgpu: add sdma v5 packet header file
Defines the SDMA packet formats.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:38 -05:00
Huang Rui
1f43631be5 drm/amdgpu: add gfx v10 clear state header v2
Clear state for gfx pipe.

v2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:37 -05:00
Huang Rui
a9833d02b5 drm/amdgpu: add v10 structs header (v2)
Header for CP structures (MQD, etc.)

V2: squash in updates

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:37 -05:00
Hawking Zhang
35c2e91059 drm/amdgpu: parse the new members added by gpu_info ucode v1_1
Parse the new parameters for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:16 -05:00
Hawking Zhang
109c80ddb4 drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10
two new members that specific for navi10 are included in v2_0:
num_sc_per_sh and num_packer_per_sc

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:16:11 -05:00
Huang Rui
23c6268eb1 drm/amdgpu: add navi10 gpu info firmware
gpu info firmware stores configuration data for various
IP blocks.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:15:29 -05:00
Hawking Zhang
3e514732c0 drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_override
New gfx config parameter.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:15:01 -05:00
Hawking Zhang
02a9e40a83 drm/amdgpu: add gfx10 specific config in amdgpu_gfx_config
The two members are used to cache the values from gpu_info fw accordingly

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:14:57 -05:00
Hawking Zhang
5228fe3010 drm/amdgpu: Add GDDR6 in vram_name arrary
For printing vram type.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 21:14:54 -05:00
Huang Rui
852a6626d5 drm/amdgpu: add navi10 asic type
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:56 -05:00
Hawking Zhang
33934b3576 drm/amdgpu: add navi10 ip offset header
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:53 -05:00
Hawking Zhang
76a2d0b0a1 drm/amdgpu: add doorbell assignement for navi10
Update mappings for Navi10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:51 -05:00
Hawking Zhang
10e4b22735 drm/amdgpu: atomfirmware.h updates for navi10
Updated tables for Navi10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:48 -05:00
Hawking Zhang
efd8725f03 drm/amdgpu: add navi10 enums header
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:46 -05:00
Hawking Zhang
d2996831b2 drm/amdgpu: add SMUIO 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:44 -05:00
Hawking Zhang
3d220cc3bd drm/amdgpu: add OSS 5.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:42 -05:00
Hawking Zhang
f519f0be45 drm/amdgpu: add MMHUB 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:39 -05:00
Hawking Zhang
be4008b8c5 drm/amdgpu: add GC 10.1 register headers (v4)
v2: Update regs (Alex)
v3: More updates (Alex)
v4: more updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:35 -05:00
Hawking Zhang
326354fa97 drm/amdgpu: add VCN 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:33 -05:00
Hawking Zhang
9edefe7bac drm/amdgpu: add NBIO 2.3 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:31 -05:00
Hawking Zhang
d33ad04027 drm/amdgpu: add MP 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:28 -05:00
Hawking Zhang
2a3196f1f0 drm/amdgpu: add HDP 5.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:26 -05:00
Hawking Zhang
d6ad5023e8 drm/amdgpu: add DCN 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:23 -05:00
Hawking Zhang
ae213c4450 drm/amdgpu: add CLK 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:21 -05:00
Hawking Zhang
db3239f535 drm/amdgpu: add ATHUB 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 15:54:18 -05:00
Alex Deucher
4f0793989f Revert "drm/amd/display: Copy stream updates onto streams"
This reverts commit 6e5155ae6b.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 12:30:01 -05:00
Alex Deucher
1a1da391c9 Revert "drm/amd/display: Use macro for invalid OPP ID"
This reverts commit 1760bd06c8.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 12:29:08 -05:00
Alex Deucher
ecbc382c9f Revert "drm/amd/display: Rework CRTC color management"
This reverts commit 7cd4b70091.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 12:27:54 -05:00
Alex Deucher
f94ec6f8b8 Revert "drm/amd/display: move vmid determination logic out of dc"
This reverts commit 11cd74cdb9.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 12:26:57 -05:00
Alex Deucher
0198b6e5be Revert "drm/amd/display: Add Underflow Asserts to dc"
This reverts commit 9ed43ef84d.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 12:25:54 -05:00
Alex Deucher
76d981a9fe Revert "drm/amd/display: make clk_mgr call enable_pme_wa"
This reverts commit a1651530a3.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 12:24:18 -05:00
Nicholas Kazlauskas
70a1efac71 Revert "drm/amd/display: Enable fast plane updates when state->allow_modeset = true"
This reverts commit ebc8c6f18322ad54275997a888ca1731d74b711f.

There are still missing corner cases with cursor interaction and these
fast plane updates on Picasso and Raven2 leading to endless PSTATE
warnings for typical desktop usage depending on the userspace.

This change should be reverted until these issues have been resolved.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110949
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:38:53 -05:00
Jack Zhang
a95ecb653a drm/amdgpu/sriov: fix Tonga load driver failed
Tonga sriov need to use smu to load firmware.
Remove sriov flag because the default return value is zero.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Trigger Huang <Trigger.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:36:45 -05:00
Jonathan Kim
9c7c85f7ea drm/amdgpu: add pmu counters
adding perf event counters

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:36:22 -05:00
Jonathan Kim
e4cf4bf5b8 drm/amdgpu: update df_v3_6 for xgmi perfmons (v2)
add pmu attribute groups and structures for perf events.
add sysfs to track available df perfmon counters
fix overflow handling in perfmon counter reads.

v2: squash in fix (Alex)

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:35:45 -05:00
Roman Li
496091fa04 drm/amd/display: Fix null-deref on vega20 with xgmi
[Why]
After clkmgr rework it gets initialized after resource pool.
The clkmgr is used in resource pool init for xgmi path.
That causes driver crash on Vega20 with xgmi due to NULL deref.

[How]
Move xgmi compensation code to dce121_clk_mgr_construct()
That also allows to make dce121_clock_patch_xgmi_ss_info()
internal static function.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:34:32 -05:00
Kent Russell
de9f26bbd3 drm/amdkfd: Add procfs-style information for KFD processes
Add a folder structure to /sys/class/kfd/kfd/ called proc which contains
subfolders, each representing an active KFD process' PID, containing 1
file: pasid.

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:34:00 -05:00
Philip Yang
e82fdb16a0 drm/amdgpu: improve HMM error -ENOMEM and -EBUSY handling
Under memory pressure, hmm_range_fault may return error code -ENOMEM
or -EBUSY, change pr_info to pr_debug to remove unnecessary kernel log
message because we will retry restore again.

Call get_user_pages_done if TTM get user pages failed will have
WARN_ONCE kernel calling stack dump log.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:33:41 -05:00
Tom St Denis
c1d827d62f drm/amd/amdgpu: cast mem->num_pages to 64-bits when shifting (v2)
On 32-bit hosts mem->num_pages is 32-bits and can overflow
when shifted.  Add a cast to avoid this.

(v2): Style fix.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:32:24 -05:00
xinhui pan
acb05f0a3f drm/amdgpu: Do error injection even vram reserve fails
As long as the address is mapped with vram, we can do an error
injection.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20 11:32:10 -05:00
Alex Deucher
21a249ca02 drm/amdgpu: wait to fetch the vbios until after common init
We need the asic_funcs set for the get rom callbacks in some
cases.

Tested-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 11:02:03 -05:00
Markus Elfring
b934152170 drm/amd/powerplay: Delete a redundant memory setting in vega20_set_default_od8_setttings()
The memory was set to zero already by a call of the function “kzalloc”.
Thus remove an extra call of the function “memset” for this purpose.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 11:02:03 -05:00
Markus Elfring
4fe7d1a8a4 drm/amd/display: Delete a redundant memory setting in amdgpu_dm_irq_register_interrupt()
The memory was set to zero already by a call of the function “kzalloc”.
Thus remove an extra call of the function “memset” for this purpose.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 11:02:03 -05:00
Arnd Bergmann
e1a2f2d23a drm/amdgpu: fix error handling in df_v3_6_pmc_start
When df_v3_6_pmc_get_ctrl_settings() fails for some reason, we
store uninitialized data in a register, as gcc points out:

drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function 'df_v3_6_pmc_start':
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1012:29: error: 'lo_val' may be used uninitialized in this function [-Werror=maybe-uninitialized]
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
                             ^~~~
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:334:39: note: 'lo_val' was declared here
  uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
                                       ^~~~~~

Make it return a proper error code that we can catch in the caller.

Fixes: 992af942a6 ("drm/amdgpu: add df perfmon regs and funcs for xgmi")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-17 11:02:03 -05:00