3 Commits

Author	SHA1	Message	Date
Andy Shevchenko	934891b0a1	dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit ... Intel iDMA 32-bit doesn't have a concept of bus masters and thus there is no need to setup any kind of masters in the CTL_LO register. Moreover, the burst size for memory-to-memory transfer is not what is says, we need to have a corrected list of possible sizes. Note, that the size of 8 items, each of that up to 4 bytes, is chosen because of maximum of 1/2 FIFO, which is 64 bytes on Intel Merrifield. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>	2019-01-07 17:57:13 +05:30
Andy Shevchenko	91f0ff883e	dmaengine: dw: Reset DRAIN bit when resume the channel ... For Intel iDMA 32-bit the channel can be drained on a suspend. We need to reset the bit on the resume to return a status quo. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>	2019-01-07 17:57:13 +05:30
Andy Shevchenko	69da8be90d	dmaengine: dw: Split DW and iDMA 32-bit operations ... Here is a kinda big refactoring that should have been done in the first place, when Intel iDMA 32-bit support appeared. It splits operations which are different to Synopsys DesignWare and Intel iDMA 32-bit controllers. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>	2019-01-07 17:57:13 +05:30