Commit Graph

8 Commits

Author SHA1 Message Date
Thomas Gleixner
3fb250ed39 gpio/msic: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-gpio@vger.kernel.org
2015-06-25 11:56:50 +02:00
Wolfram Sang
4a3a950ee9 gpio: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:31 +02:00
Linus Walleij
9fb1f39eb2 gpio/pinctrl: make gpio_chip members typed boolean
This switches the two members of struct gpio_chip that were
defined as unsigned foo:1 to bool, because that is indeed what
they are. Switch all users in the gpio and pinctrl subsystems
to assign these values with true/false instead of 0/1. The
users outside these subsystems will survive since true/false
is 1/0, atleast we set some kind of more strict typing example.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-04 14:42:46 +01:00
Linus Walleij
e5428a682c gpio: drop users of irq_set_chip_and_handler_name()
Switch all users of irq_set_chip_and_handler_name() to simply
use irq_set_chip_and_handler(), all just provide a boilerplate
name like "demux" or "mux" - a fact which is anyway obvious
from the hwirq number from the irqdomain now present in e.g.
/proc/interrupts.

Cc: Mathias Nyman <mathias.nyman@linux.intel.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: David Cohen <david.a.cohen@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-03 11:25:47 +01:00
Jingoo Han
e56aee1897 gpio: use dev_get_platdata()
Use the wrapper function for retrieving the platform data instead of
accessing dev->platform_data directly.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-16 15:24:35 +02:00
Bill Pemberton
3836309d93 gpio: remove use of __devinit
CONFIG_HOTPLUG is going away as an option so __devinit is no longer
needed.

Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-28 11:39:33 -08:00
Axel Lin
f7da0bdbf5 gpio: msic: Fix calculating register address in msic_gpio_to_oreg()
In the case offset is 20 ... 23, the equation to get the register should be:
        INTEL_MSIC_GPIO1HV0CTLO - offset + 20

With above equation, we can get below mapping between offset and the register:
        offset is 20: INTEL_MSIC_GPIO1HV0CTLO
        offset is 21: INTEL_MSIC_GPIO1HV1CTLO
        offset is 22: INTEL_MSIC_GPIO1HV2CTLO
        offset is 23: INTEL_MSIC_GPIO1HV3CTLO

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-08-05 01:09:50 +02:00
Mathias Nyman
25cf25073a gpio: add MSIC gpio driver
Add gpio support for Intel MSIC chips found in Intel Medfield platforms.
MSIC supports totally 24 GPIOs with 16 low voltage and 8 high voltage pins.
Driver uses MSIC mfd interface for MSIC access.

(Updated comment to indicate why locking is actually safe)

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-05-11 13:14:54 -06:00