Commit Graph

58 Commits

Author SHA1 Message Date
Dan Carpenter
73061da07d intel_th: Check for NULL instead of ERR_PTR
devm_ioremap() returns NULL on error, it doesn't return an ERR_PTR,
which is what the current code does. This patch corrects these
checks.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-16 23:25:48 -07:00
Alexander Shishkin
1c090575b0 stm class: Select configfs
STM policy handling is basically configfs, I honestly don't know how we
ended up without a Kconfig dependency, but thanks to randconfig testing,
it's now caught.

Reported-by: Jim Davis <jim.epost@gmail.com>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-16 23:25:48 -07:00
Alexander Shishkin
ed392688b5 intel_th: Fix integer mismatch warnings
Use unsigned long in place of size_t to operate on buffer sizes and
offsets to clean up the 32 bit build.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-10 12:24:47 -07:00
Alexander Shishkin
0df771dedf stm class: Mark src::link __rcu
Source device's link is protected with srcu, mark it as such to have
proper build-time validation of accesses to this field. The update
side that's dereferencing it under an update lock also needs an
accessor to dereference this field to keep sparse happy.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-10 12:24:47 -07:00
Mathieu Poirier
af6162155e coresight: etm3x: making error message unambiguous
By adding the function name at the beginning of the error
message there is no doubt as to where the failing condition
occurred.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 17:54:09 +01:00
Mathieu Poirier
7253e4c956 coresight: etm3x: breaking down sysFS status interface
SysFS rules stipulate that only one value can be conveyed per
file.  As such splitting the "status" interface in individual files.

This is also useful for user space applications - that way they can
probe each file individually rather than having to parse a list of entries.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 17:54:09 +01:00
Mathieu Poirier
adfad8745c coresight: etm3x: adding cpu affinity to sysFS interface
Without access to the device tree, it is impossible to know
what CPU a tracer is affined to.  As such adding a new sysFS
interface to convey the information.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 17:54:09 +01:00
Mathieu Poirier
58b8d51b84 coresight: adding comments to remove ambiguity
Add comment to function coresight_enable_path() to make
sure there is no misunderstanding about what the code does.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 17:54:09 +01:00
Chunyan Zhang
497b59565b Coresight: ETMv4: Prevent TRCRSCTLR0&1 from being accessed
1. TRCRSCTLRn - Resource Selection Control Registers n=0~1 are reserved,
   we shouldn't access them.
2. The max number of 'n' here is defined in TRCIDR4.NUMRSPAIR whoes value
   indicates the number of resource selection *pairs*, and 0 indicates
   one resource selection pair, 1 indicates two pairs, and so on ...

So, the total number of resource selection control registers which we can
access is (TRCIDR4.NUMRSPAIR * 2)

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07 17:54:09 +01:00
Alexander Shishkin
14cdbf0417 intel_th: Add PTI output driver
Parallel Trace Interface (PTI) unit is a trace output device that sends
data over a PTI port.

The driver provides interfaces to configure bus width, bus clock divider
and mode. Tracing is enabled via output device's "active" attribute.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
ba82664c13 intel_th: Add Memory Storage Unit driver
Memory Storage Unit (MSU) is a trace output device that collects trace
data to system memory. It consists of 2 independent Memory Storage
Controllers (MSCs).

This driver provides userspace interfaces to configure in-memory tracing
parameters, such as contiguous (high-order allocation) buffer or multiblock
(scatter list) buffer mode, wrapping (data overwrite) and number and sizes
of windows in multiblock mode. Userspace can read the buffers via mmap()ing
or read()ing of the corresponding device node.

Signed-off-by: Laurent Fert <laurent.fert@intel.com>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
f04e449fc7 intel_th: Add Software Trace Hub driver
Software Trace Hub (STH) is a trace source device in the Intel TH
architecture, it generates data that then goes through the switch into
one or several output ports.

STH collects data from software sources using the stm device class
abstraction.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
b27a6a3f97 intel_th: Add Global Trace Hub driver
Global Trace Hub (GTH) is the central component of Intel TH architecture;
it carries out switching between the trace sources and trace outputs, can
enable/disable tracing, perform STP encoding, internal buffering, control
backpressure from outputs to sources and so on.

This property is also reflected in the software model; GTH (switch) driver
is required for the other subdevices to probe, because it matches trace
output devices against its output ports and configures them accordingly.

It also implements an interface for output ports to request trace enabling
or disabling and a few other useful things.

For userspace, it provides an attribute group "masters", which allows
configuration of per-master trace output destinations for up to master 255
and "256+" meaning "masters 256 and above". It also provides an attribute
group to discover and configure some of the parameters of its output ports,
called "outputs". Via these the user can set up data retention policy for
an individual output port or check if it is in reset state.

Signed-off-by: Laurent Fert <laurent.fert@intel.com>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
2b0b16d329 intel_th: Add pci glue layer for Intel(R) Trace Hub
This patch adds basic support for PCI-based Intel TH devices. It requests
2 bars (configuration registers for the subdevices and STH channel MMIO
region) and calls into Intel TH core code to create the bus with subdevices
etc.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
39f4034693 intel_th: Add driver infrastructure for Intel(R) Trace Hub devices
Intel(R) Trace Hub (TH) is a set of hardware blocks (subdevices) that
produce, switch and output trace data from multiple hardware and
software sources over several types of trace output ports encoded
in System Trace Protocol (MIPI STPv2) and is intended to perform
full system debugging.

For these subdevices, we create a bus, where they can be discovered
and configured by userspace software.

This patch creates this bus infrastructure, three types of devices
(source, output, switch), resource allocation, some callback mechanisms
to facilitate communication between the subdevices' drivers and some
common sysfs attributes.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
e3e5a3d3da stm class: stm_console: Add kernel-console-over-stm driver
This is a simple stm_source class device driver (kernelspace stm trace
source) that registers a console and sends kernel messages over STM
devices.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
2c41538191 stm class: dummy_stm: Add dummy driver for testing stm class
This is a simple module that pretends to be an stm device and discards
all the data that comes in. Useful for testing stm class and its users.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Alexander Shishkin
7bd1d4093c stm class: Introduce an abstraction for System Trace Module devices
A System Trace Module (STM) is a device exporting data in System Trace
Protocol (STP) format as defined by MIPI STP standards. Examples of such
devices are Intel(R) Trace Hub and Coresight STM.

This abstraction provides a unified interface for software trace sources
to send their data over an STM device to a debug host. In order to do
that, such a trace source needs to be assigned a pair of master/channel
identifiers that all the data from this source will be tagged with. The
STP decoder on the debug host side will use these master/channel tags to
distinguish different trace streams from one another inside one STP
stream.

This abstraction provides a configfs-based policy management mechanism
for dynamic allocation of these master/channel pairs based on trace
source-supplied string identifier. It has the flexibility of being
defined at runtime and at the same time (provided that the policy
definition is aligned with the decoding end) consistency.

For userspace trace sources, this abstraction provides write()-based and
mmap()-based (if the underlying stm device allows this) output mechanism.

For kernel-side trace sources, we provide "stm_source" device class that
can be connected to an stm device at run time.

Cc: linux-api@vger.kernel.org
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-04 20:28:58 +01:00
Chunyan Zhang
f67b467aab coresight-etm4x: Support context-ID tracing when PID namespace is enabled
Like ETTv3, ETMv4 also needs the similar modifications to support Context
ID tracing when PID namespace is enabled.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-05 13:30:15 -07:00
Chunyan Zhang
a440617e0d coresight-etm3x: Support context-ID tracing when PID namespace is enabled
The Coresight ETM drivers already support context-ID tracing, but it won't
work when PID namespace is enabled. This is because when using PID
namespace a process id (ie. VPID) seen from the current namespace differs
from the id (ie. PID) seen by kernel.

So when users write the process id seen by themselves to ETM, there needs
to be a translation from VPID to PID, as such ETM drivers will write the
PID into the Context ID register correctly.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-05 13:30:15 -07:00
Chunyan Zhang
cd196ac3fa coresight-etm4x: Change the name of the ctxid_val to ctxid_pid
'ctxid_val' array was used to store the value of ETM context ID comparator
which actually stores the process ID to be traced, so using 'ctxid_pid' as
its name instead make it easier to understand.

This patch also changes the ABI, it is normally not allowed, but
fortunately it is a testing ABI and very new for now. Nevertheless,
if you don't think it should be changed, we could always add an alias
for userspace.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-05 13:30:15 -07:00
Chunyan Zhang
414a1417d7 coresight-etm3x: Change the name of the ctxid_val to ctxid_pid
'ctxid_val' array was used to store the value of ETM context ID comparator
which actually stores the process ID to be traced, so using 'ctxid_pid' as
its name instead make it easier to understand.

This patch also changes the ABI, it is normally not allowed, but
fortunately it is a testing ABI and very new for now. Nevertheless,
if you don't think it should be changed, we could always add an alias
for userspace.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-05 13:30:15 -07:00
Vaishali Thakkar
c35aaa1379 coresight: replicator: Use builtin_platform_driver()
Macro builtin_platform_driver can be used for builtin drivers
that don't do anything in driver init. This file depends on
Kconfig CONFIG_CORESIGHT_LINKS_AND_SINKS which eventually
depends on CORESIGHT. Both CONFIG_CORESIGHT_LINKS_AND_SINKS and
CORESIGHT are bool. So, use builtin_platform_driver and remove
some boilerplate code.

Also, remove header file init.h as functionality like module_init
and module_exit is now relocated to module.h.

Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com>
Suggested-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-05 13:30:15 -07:00
Ivan T. Ivanov
27d3fd3d0d coresight-etm3x: Add Qualcomm PTM v1.1 peripheral ID
Add Qualcomm's PTM v1.1 peripheral ID to supported devices.
This device could be found at least in MSM8974 and APQ8064
chipsets.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-05 13:30:15 -07:00
Paul Gortmaker
fc368ea1ea drivers/hwtracing: fix coresight-etm4x implicit <module.h> usage
In commit 2e1cdfe184 ("coresight-etm4x:
Adding CoreSight ETM4x driver") this driver was added.

It uses module_amba_driver() to register itself with the system,
which is just an alias for module_driver.  This currently works by
relying on getting that via init.h but we are planning to move that
code[1] to module.h -- at which time this will fail to compile since
it does not include module.h currently, resulting in:

drivers/hwtracing/coresight/coresight-etm4x.c:2701:1: note: in expansion of macro ‘module_amba_driver’
 module_amba_driver(etm4x_driver);
 ^
include/linux/device.h:1296:1: error: type defaults to ‘int’ in declaration of ‘module_init’ [-Werror=implicit-int]
 module_init(__driver##_init); \
 ^

In the future, the amba support may want to create another alias that
uses builtin_driver[2] for cases like this which are using bool Kconfig
triggers, but for now we just fix the implicit include.

[1] https://lkml.kernel.org/r/1433276168-21550-1-git-send-email-paul.gortmaker@windriver.com
[2] https://lkml.kernel.org/r/1431287385-1526-1-git-send-email-paul.gortmaker@windriver.com

Cc: Pratik Patel <pratikp@codeaurora.org>
Cc: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-06-08 13:46:43 -07:00
Paul Gortmaker
5a6a7cd05c drivers/hwtracing: fix coresight-replicator-qcom implicit <module.h> usage
In commit 620cf787c1 ("coresight: replicator:
Add Qualcomm CoreSight Replicator driver") this driver was added.

It uses module_amba_driver(replicator_driver) to register itself with
the system -- which is just an alias for module_driver.  This currently
works by relying on getting that via init.h but we are planning to move
that code[1] to module.h -- at which time this will fail to compile since
it does not include module.h currently, resulting in:

drivers/hwtracing/coresight/coresight-replicator-qcom.c:214:1: error: type defaults to 'int' in declaration of 'module_init' [-Werror=implicit-int]
drivers/hwtracing/coresight/coresight-replicator-qcom.c:214:1: error: type defaults to 'int' in declaration of 'module_exit' [-Werror=implicit-int]

In the future, the amba support may want to create another alias that
uses builtin_driver[2] for cases like this which are using bool Kconfig
triggers, but for now we just fix the implicit include.

[1] https://lkml.kernel.org/r/1433276168-21550-1-git-send-email-paul.gortmaker@windriver.com
[2] https://lkml.kernel.org/r/1431287385-1526-1-git-send-email-paul.gortmaker@windriver.com

Cc: Pratik Patel <pratikp@codeaurora.org>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-06-08 13:46:43 -07:00
Pratik Patel
620cf787c1 coresight: replicator: Add Qualcomm CoreSight Replicator driver
This driver manages Qualcomm CoreSight Replicator device, which
resides on the AMBA bus. Replicator has been made programmable to
allow software to turn of the replicator branch to sink that is not
being used. This avoids trace traffic to the unused/non-current sink
from causing back pressure that results in overflows at the source.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Pankaj Dubey
437012368c coresight: fix typo in of_coresight.c
fixes obvious typo in of_coresight.c
%s/non-configuable/non-configurable

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
9875cd9ce2 coresight: replicator: retrieve and handle atclk
As can be seen from the datasheet of the CoreSight
Components, DDI0314 table A-4 the funnel has a clock signal
apart from the AHB interconnect ("amba_pclk", that we're
already handling) called ATCLK, ARM Trace Clock, that SoC
implementers may provide from an entirely different clock
source. So to model this correctly create an optional
path for handling ATCLK alongside the PCLK so we don't
break old platforms that only define PCLK ("amba_pclk") but
still makes it possible for SoCs that have both clock signals
(such as the DB8500) to fetch and prepare/enable/disable/
unprepare both clocks.

The ATCLK is enabled and disabled using the runtime PM
callbacks. As the replicator is a platform device, the
code is a bit different from the other CoreSight components
and the bus core does not activate runtime PM by default,
so we need a few extra calls.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
2e5f75d1a4 coresight: funnel: retrieve and handle atclk
As can be seen from the datasheet of the CoreSight
Components, DDI0314 table A-6 the funnel has a clock signal
apart from the AHB interconnect ("amba_pclk", that we're
already handling) called ATCLK, ARM Trace Clock, that SoC
implementers may provide from an entirely different clock
source. So to model this correctly create an optional
path for handling ATCLK alongside the PCLK so we don't
break old platforms that only define PCLK ("amba_pclk") but
still makes it possible for SoCs that have both clock signals
(such as the DB8500) to fetch and prepare/enable/disable/
unprepare both clocks.

The ATCLK is enabled and disabled using the runtime PM
callbacks.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
267b2c2358 coresight: etb: retrieve and handle atclk
As can be seen from the datasheet of the CoreSight
Components, DDI0314 table A-8 the ETB has a clock signal
apart from the AHB interconnect ("amba_pclk", that we're
already handling) called ATCLK, ARM Trace Clock, that SoC
implementers may provide from an entirely different clock
source. So to model this correctly create an optional
path for handling ATCLK alongside the PCLK so we don't
break old platforms that only define PCLK ("amba_pclk") but
still makes it possible for SoCs that have both clock signals
(such as the DB8500) to fetch and prepare/enable/disable/
unprepare both clocks.

The ATCLK is enabled and disabled using the runtime PM
callbacks.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
db341d3d51 coresight: tpiu: retrieve and handle atclk
As can be seen from the datasheet of the CoreSight
Components, DDI0314H page A-19 the TPIU has a clock signal
apart from the AHB interconnect ("amba_pclk", that we're
already handling) called ATCLK, ARM Trace Clock, that SoC
implementers may provide from an entirely different clock
source. So to model this correctly create an optional
path for handling ATCLK alongside the PCLK so we don't
break old platforms that only define PCLK ("amba_pclk") but
still makes it possible for SoCs that have both clock signals
(such as the DB8500) to fetch and prepare/enable/disable/
unprepare both clocks in conjunction.

The ATCLK is enabled and disabled using the runtime PM
callbacks.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
d1839e6877 coresight: etm: retrieve and handle atclk
As can be seen from the datasheet of the CoreSight
Components, DDI0401C A.1.1 the ETM has a clock signal
apart from the AHB interconnect ("amba_pclk", that we're
already handling) called ATCLK, ARM Trace Clock, that SoC
implementers may provide from an entirely different clock
source. So to model this correctly create an optional
path for handling ATCLK alongside the PCLK so we don't
break old platforms that only define PCLK ("amba_pclk") but
still makes it possible for SoCs that have both clock signals
(such as the DB8500) to fetch and prepare/enable/disable/
unprepare both clocks.

The ATCLK is enabled and disabled using the runtime PM
callbacks.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
32398ef6f4 coresight: tmc: let runtime PM handle core clock
This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will unprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.

Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
the clk_prepare_enable() and clk_disable_unprepare() was
called and thus just increase and decreas the refcount by
one, without it reaching zero and actually disabling the
clock. Now the runtime PM callbacks will make sure the PCLK
is properly disabled after probe.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
e2d08f96d4 coresight: funnel: let runtime PM handle core clock
This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will unprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.

Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
clk_disable_unprepare() was not called. Now the runtime PM
callbacks will make sure the PCLK is properly disabled
after probe.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
1b19f59dca coresight: etb: let runtime PM handle core clock
This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will unprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.

Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
the clk_prepare_enable() and clk_disable_unprepare() was
called and thus just increase and decreas the refcount by
one, without it reaching zero and actually disabling the
clock. Now the runtime PM callbacks will make sure the PCLK
is properly disabled after probe.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
b5913d6436 coresight: tpiu: let runtime PM handle core clock
This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will unprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.

Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
the clk_prepare_enable() and clk_disable_unprepare() was
called and thus just increase and decreas the refcount by
one, without it reaching zero and actually disabling the
clock. Now the runtime PM callbacks will make sure the PCLK
is properly disabled after probe.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:08 -07:00
Linus Walleij
ec36005910 coresight: etm: let runtime PM handle core clock
This uses runtime PM to manage the PCLK ("amba_pclk") instead
of screwing around with the framework by going in and taking
a copy from the amba device. The amba bus core will unprepare
and disable the clock when the device is unused when
CONFIG_PM is selected, else the clock will be always on.

Prior to this patch, as the AMBA primecell bus code enables
the PCLK, it would be left on after probe as
the clk_prepare_enable() and clk_disable_unprepare() was
called and thus just increase and decreas the refcount by
one, without it reaching zero and actually disabling the
clock. Now the runtime PM callbacks will make sure the PCLK
is properly disabled after probe.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:07 -07:00
Linus Walleij
4339b69997 coresight: support the TPIU version found in Ux500
The Ux500 has a PrimeCell version 4B instead of the 3B as
supported by the driver, extend the match table to cover
this version.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:07 -07:00
Linus Walleij
1c65b3885a coresight: etm: print what version of ETM/PTM is detected
Helpfully report a bit more about the hardware found in the
silicon when matching the AMBA device IDs by using the associated
.data pointer in the AMBA match.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:07 -07:00
Mathieu Poirier
899867ee6c coresight-etm3x: use module_amba_driver to simplify the code
Using function "module_amba_driver()" makes the code simpler by
eliminating boilerplate code.

Wei Yongjun sent out a set of patches addressing those in all the
coresight driver but missed ETMv3.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:12:07 -07:00
Mathieu Poirier
5625988e1e coresight-etm4x: Read only access to the tracer's ID registers
ETM ID registers contain valuable information about the capabilities
of the implementation and are very useful when configuring the device for
various trace scenarios.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Mathieu Poirier
a467dae11d coresight-etm4x: Read only access to the main management registers
Having access to the ETMv4 management registers is very useful as they
give meaningful information on how the IP block has been configured at
synthesis time.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Pratik Patel
40d8ebf071 coresight-etm4x: Controls pertaining to the VM ID functions
Adding sysfs entries to access and configure specifics about the
virtual machine ID comparator functions.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Pratik Patel
4a584be1d0 coresight-etm4x: Controls pertaining to the context ID functions
Adding sysfs entries to access and configure specifics about the
context ID comparator functions.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Pratik Patel
6afa8a1387 coresight-etm4x: Controls pertaining to the selection of resources
Adding sysfs entries to control the selection of the resources the
trace unit will use as triggers to perform a trace run.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Pratik Patel
add2d5d0d1 coresight-etm4x: Controls pertaining to the counter functions
Adding sysfs entries related to the counter functionality, more
specifically to set, control and reload the counters.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Pratik Patel
5e5ff34406 coresight-etm4x: Controls pertaining to the sequencer functions
Adding sysfs entries to access the sequencers related registers,
more specifically the sequencer state, the sequencer state
transition and the sequencer reset control registers.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:21 -07:00
Pratik Patel
35c9b29bc8 coresight-etm4x: Controls pertaining to the address comparator functions
Adding sysfs entries to control the various mode the address comparator
registers can enact, i.e, start/top, single, and range.  Also supplementing
with address comparator types configuration registers access, mandatory
to complete the configuration of the comparator functions.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:20 -07:00
Pratik Patel
43ba6a7b00 coresight-etm4x: Controls pertaining to the ViewInst register
Adding sysfs entries to control the ViewInst register's event
selector along with secure and non-secure exception level
instruction tracing.

Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-24 11:11:20 -07:00