* RZ/G1C (r8a77470) SoC: Use r8a77470-cpg-mssr binding definitions
* Add GR-Peach audio camera shield support with MT9V111 image sensor
* Add initial support for RZ/N1D (r9a06g032) SoC and its RZN1D-DB board
* Use SPDX identifiers in DT for all SoCs and boards
* Add missing OPP properties for all CPUs on various SoCs
* Add missing PMIC nodes to R-Car Gen2 M2-W (r8a7791) based porter board
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAltVvhcACgkQ189kaWo3
T76ABRAAsWkpVoxzMSj9c+qPtQ4r6aUsAF/gQfcU5eCdc4/v4YAhSzH2npY7CJ6N
kUCdqLXtOI/1CvNUL9jg/BSl88oiObryFlfhAWsiraN82yTp6426YfCFAht9Hynx
8hjEnp6M0D9dl6hKuA9Qn9V1PgM17nVLkuCkaCI1mgd3J0MNyUV0BGQJxZ+2/QmE
LfXmBywDgTtyrLiwpTWwRZT290X0xYMTHJnew4c7m7JSqlHi38EZJ3r/VqD/Cwkk
0fk/IDS4w9UFlwV326bjxyoozTnajgrcW6Gb40VPQYnJ+rD9FqnhPJilXhavJ/t/
AGNc9r8wMkYVwwfcYNvW9m1plfmpxiYulvOX6TKBp22yM0QiqLpu1C5gjSAce5i/
VH61eBDUYYMdXLtQfLoEv91pmJZmrWGs0IRSGHdaNSOUYyW3FtBBTIvfmpbB09JU
FNPCG1YFrCCndDKWPieYx056fydChYNK6S2a9nrAK97h5WiPxOpBnDET9dHkUMod
n50r+9Qr4ty68oOyJPqtHnSk3d5AU42I4iwSoiNLgbBWbvBLlmFe3Ov3B53rdVLD
DJ7ixGKYz1XaAuWDd72NVpDqeU60vVuvJJx+GOSIq0KXXn74ajcB/g4fekn/ZXMK
43gUB5MSzemgpRNmZi6Z78HF5ZmvQsCcl3yXuepdW0/k8CypVtk=
=jxlx
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.19
* RZ/G1C (r8a77470) SoC: Use r8a77470-cpg-mssr binding definitions
* Add GR-Peach audio camera shield support with MT9V111 image sensor
* Add initial support for RZ/N1D (r9a06g032) SoC and its RZN1D-DB board
* Use SPDX identifiers in DT for all SoCs and boards
* Add missing OPP properties for all CPUs on various SoCs
* Add missing PMIC nodes to R-Car Gen2 M2-W (r8a7791) based porter board
* tag 'renesas-arm-dt-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r8a77470: Use r8a77470-cpg-mssr binding definitions
ARM: dts: gr-peach: Add GR-Peach audiocamerashield support
ARM: dts: Renesas R9A06G032 SMP enable method
ARM: dts: Renesas RZN1D-DB Board base file
ARM: dts: Renesas R9A06G032 base device tree file
ARM: dts: convert to SPDX identifier for Renesas boards
ARM: dts: r8a77(43|9[013]): Add missing OPP properties for CPUs
ARM: dts: porter: Add missing PMIC nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
This turns on the FSI-attached I2C bus driver, and the ColdFire
offloaded FSI master which are new to 4.19.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Building on arm 32 with LPAE enabled we don't include asm-generic/tlb.h,
where we have tlb_flush_remove_tables_local and tlb_flush_remove_tables
defined.
The build fails with:
mm/memory.c: In function ‘tlb_remove_table_smp_sync’:
mm/memory.c:339:2: error: implicit declaration of function ‘tlb_flush_remove_tables_local’; did you mean ‘tlb_remove_table’? [-Werror=implicit-function-declaration]
...
This bug got introduced in:
2ff6ddf19c ("x86/mm/tlb: Leave lazy TLB mode at page table free time")
To fix this issue we define them in arm 32's specific asm/tlb.h file as well.
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: dave.hansen@intel.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@armlinux.org.uk
Cc: riel@surriel.com
Cc: songliubraving@fb.com
Fixes: 2ff6ddf19c ("x86/mm/tlb: Leave lazy TLB mode at page table free time")
Link: http://lkml.kernel.org/r/20180725095557.19668-1-anders.roxell@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Add a node for the CVIC (the coprocessor interrupt controller) and
add a label to the SRAM node so it can be referenced from the board
device-tree file.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This enables the devices used in the AST2400 family of BMC SoCs:
- VUART
- SPI NOR
- LPC controller
- LPC snoop (port 80)
- Ethernet
- GPIO
- ADC
- I2C
- Random number generator
- IPMI KCS
- IPMI BT
- Fan/Tach
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This is the result of a make mutli_v5_defconfig && make savedefconfig.
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
- Enable new support:
hardware random number generator
FSI and client drivers
DRM GFX driver
- Disable unwanted features:
ARM_APPENDED_DTB
ARM_ATAG_DTB_COMPAT
BLK_DEV_RAM
- Sync G4 and G5 with OpenBMC configurations
BLK_DEV_LOOP, for updater mechanic
CRYPTO_HMAC, for libsdbus features
CRYPTO_SHA256
CRYPTO_USER_API_HASH
- Enable security related features:
SLAB_FREELIST_RANDOM
STRICT_KERNEL_RW
CC_STACKPROTECTOR_STRONG
HARDENED_USERCOPY
FORTIFY_SOURCE
- Increase kernel log buffer size
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
S5Pv210 and Exynos5433/Exynos7 have different address of
EINT_WAKEUP_MASK register. Rename existing S5P_EINT_WAKEUP_MASK to
avoid confusion and add new ones.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
For most of Exynos SoCs, Power Management Unit (PMU) address space is
mapped into global variable 'pmu_base_addr' very early when initializing
PMU interrupt controller. A lot of other machine code depends on it so
when doing iounmap() on this address, clear the global as well to avoid
usage of invalid value (pointing to unmapped memory region).
Properly mapped PMU address space is a requirement for all other machine
code so this fix is purely theoretical. Boot will fail immediately in
many other places after following this error path.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The current maintainers are specified in MAINTAINERS file, so remove
in-sources information with outdated e-mail address (Thomas Abraham's
email does not work, Kukjin Kim uses @kernel.org).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add mali gpu node to sun4i a10 platforms.
Tested with offscreen rendering with lima mesa (freedesktop gitlab)
Signed-off-by: Steven Vanden Branden <stevenvandenbrandenstift@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This pin is externally pulled up, so we need to disable the SoC's
internal pull down resistor to allow it to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This pin is externally pulled up, so we need to disable the
SoC's internal pull-down.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This pin is externally pulled up, so we should disable the SoC's
pull down resistor in order for the interrupt to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This pins are externally pulled up, and so we should explicitly
configure them to disable the SoC-internal pull-downs. Previously
we relied on the bootloader doing this in order to allow the buttons
to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Currently, we assume that the bootloader has correctly configured
the interrupt pin for max77693. This might not actually be the case -
so it's better to configure it explicitly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Enable support for the Renesas RZN1D-DB Board:
- RZ/N1D (R9A06G032) base SoC support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Replace the hardcoded clock indices by R8A77470_CLK_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device tree header for GR-Peach's audiocamerashield with MT9V111
image sensor.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds the Renesas R9A06G032 bare bone support.
This currently only handles the SYSCTRL block note,
generic parts (gic, architected timer) and a UART.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated MAINTAINERS file
[simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing properties (like, clock latency, voltage tolerance,
etc) as well to make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
No recent mainstream system uses the /sbin/hotplug fork-bomb any more.
Commit 7934779a69 ("Driver-Core: disable
/sbin/hotplug by default") disabled it in Kconfig, but the various
defconfigs weren't updated.
According to the systemd requirements, this option must be disabled, as
it slows down the system and confuses udev.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable support for the Renesas RZN1D-DB Board:
- RZ/N1D (R9A06G032) base SoC support,
- Synopsys DesignWare 8250 serial port support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
R-Car Gen2 and RZ/G1 SoCs can make use of the optional reset controller
support in the Renesas CPG/MSSR driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enabling NET_VENDOR_* Kconfig options does not directly affect the
kernel, so there is no need to explicitly disable them.
The individual network drivers under them are still disabled.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There's one ARM, one x86_32 and one x86_64 version of efi_open_volume()
which can be folded into a single shared version by masking their
differences with the efi_call_proto() macro introduced by commit:
3552fdf29f ("efi: Allow bitness-agnostic protocol calls").
To be able to dereference the device_handle attribute from the
efi_loaded_image_t table in an arch- and bitness-agnostic manner,
introduce the efi_table_attr() macro (which already exists for x86)
to arm and arm64.
No functional change intended.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/20180720014726.24031-7-ard.biesheuvel@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
- Fix interrupt type on ethernet switch for i.MX-based RDU2
- GPC on i.MX exposed too large a register window which resulted in
userspace being able to crash the machine.
- Fixup of bad merge resolution moving GPIO DT nodes under pinctrl
on droid4.
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAltToboPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3gP4P/3Mntu351wZpaczDQZFQxSvxnmT2Ocr9YKFR
u5UOoE1hTCxOHcrZO7C/EbIKaqD1QhpxMPevcqpOid0glAiEj6D0c0qewAML2vwH
gGENHX5z5phwrK7RDJZhBiH2jKCg8ttOn0QSoHxGGZNSPAL2nimMwD0IbiqTI5dx
SkqecCPBwmizpfltdOCRRhN9RCiIvzcqoyLz0HjZ/sff1Y+t3U+alq227rZkQOki
bj9uD+XkKYZzgiECd6HfMtPHUSUusSXcpF/TyfdnHeyHpF1E3InPVC7dbTASFnxb
C6zrX99c2Fu11TV7Kkkn1LTwA0rRuXQmSV7ZWZMOqQBrONqGpy0CPIY+LA1xYGCd
8VtgP7qj0m7XKkPyEriwNDSKKE+c7cCYn9VpR6Kg5xmw0DUCTohMQmeZRo2sMylT
UlYMjNKQ53IuPullwRaJVM63kA3CuFo3fyStg18SYcx2lRFO8lcGJYqjqd91KkDF
ZW/tG9V6v7lz/3J3XUOFTJNWwi1CUKEIMM3ObtfDAZToyS1zbe5kX+kiTcUnvGty
wv3aWCknQnru++vYhtIYLsqwu/NwoJLTWppEmX4YxoV8fW4Yw95e3zjwzWn7rczQ
dNv7b4Hz/gpDZk7o3dpBpajTCzhh549bDfY9yxBpkd+otUKvgjKkKvsiqCkFV+j7
dcs5FMT5
=VFnX
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
- Fix interrupt type on ethernet switch for i.MX-based RDU2
- GPC on i.MX exposed too large a register window which resulted in
userspace being able to crash the machine.
- Fixup of bad merge resolution moving GPIO DT nodes under pinctrl on
droid4.
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: imx6: RDU2: fix irq type for mv88e6xxx switch
soc: imx: gpc: restrict register range for regmap access
ARM: dts: omap4-droid4: fix dts w.r.t. pwm
- Enable ISL29018 sensor and MMA8452 accelerometer driver support for
imx6qdl-sabreauto board.
- Enable DMATEST support which is useful for DMA driver development
testing.
- Use the DRM driver for MXSFB LCD controller found on i.MX23, i.MX28,
i.MX6SX and i.MX7 SoCs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbUpWLAAoJEFBXWFqHsHzOlSMH/3lLUjNHkZyeZ06KiOLAJ05W
dQT01yA5QZ7MBr2xBbla/4aAjiVYIkeUfbMbRsdx+XQ4p70tvA9op9U4aGOAKBzE
Coyon2ufXJAxg60MBs9VaPrP/xouJnGeKBCm2Sgvaht/e5hngMc0LOFX6bNFa/uJ
gc0r51DMHExpSV3apidgYoUKTGFoPGvTSM4Cd+mQMVdTJAQsrKSsx3w6KlzWiVlB
Pw1iiqlOkUxaON7751uCHQvebY4XYZ+G7F1kFKS2nVrUB5qtjbhbJdXBon+nBLlt
NCscfg5GTqhlIIkCrcci3sStG+kwIo01YfJxigroSZodssUm/r/9KmqnHpgSly8=
=8A9u
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/defconfig
i.MX defconfig update for 4.19:
- Enable ISL29018 sensor and MMA8452 accelerometer driver support for
imx6qdl-sabreauto board.
- Enable DMATEST support which is useful for DMA driver development
testing.
- Use the DRM driver for MXSFB LCD controller found on i.MX23, i.MX28,
i.MX6SX and i.MX7 SoCs.
* tag 'imx-defconfig-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx_v6_v7_defconfig: add DMATEST support
ARM: imx_v6_v7_defconfig: use MXSFB DRM driver
ARM: mxs_defconfig: use MXSFB DRM driver
ARM: imx_v6_v7_defconfig: Enable imx6qdl-sabreauto sensors
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add device tree support for i.MX6SLL SoC.
- New board support: ConnectCore 6UL System-On-Module and SBC Express;
ZII SCU2 Mezz, SCU3 ESB, SSMB SPU3 and CFU1 board; i.MX6SLL EVK
board; Engicam i.CoreM6 1.5 Quad/Dual MIPI; LogicPD MX31Lite board;
i.MX53 HSC/DDC boards from K+P.
- Remove fake regulator bus container node and enable USB OTG support
for i.MX6 wandboard and riotboard.
- Populate RAVE SP EEPROM, backlight, power button and watchdog devices
for ZII boards.
- Add cooling-cells for cpufreq cooling device, and add OPP properties
for all CPUs.
- A series from Anson Huang to enable LCD panel and backlight support
for imx6sll-evk board.
- Make pfuze100 sw4 regulator always-on for for a few Freescale/NXP
development boards, because the regulator is critical there and
cannot be turned off.
- Add more device support for i.MX5: AIPSTZ, SAHARA Crypto, M4IF,
Tigerp, PMU, CodaHx4 VPU.
- Enable PMU secure-reg-access for imx51-babbage, imx51-zii-rdu1 and
imx53-ppd board.
- Switch more device tree license to use SPDX identifier.
- Switch to use OF graph to describe the display for imx7d-nitrogen7.
- Add chosen/stdout-path for more boards, so that earlycon can be
enabled more easily on kernel cmdline.
- Convert GPC to new device tree bindings and add Vivante gpu nodes
for i.MX6SL SoC.
- Add more device support for imx6dl-mamoj board: parallel display,
WiFi and USB.
- A series from Stefan Agner to update i.MX6 apalis/colibri boards on
various aspects: SD/MMC card detection, regulators, etc.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbUo3SAAoJEFBXWFqHsHzOtMAH/3UgJzGvYHIiOVVTAvwz3V5y
vZibWFOmzQDUcn3nrP54wGaMHT0abQ81AwrHKr0Bj1ujeJTCglRT8N5I/Dph6emU
aDSBIlv8y1fqF/96LhDk3bqGwg/pdF29dWBsaV45Va/ZZGErEzSTNlxV/n+nHkVy
S6rjGRkqk9abGmpDdJg2gYDYisDr9dl8iAEEBzBmOWLusEL2nvrqaMEmqBtVDFYd
fwLa+4HYZF3DaIfEjYy1INHeoCyBEAk8BS9u7b1jWTxONLNXh5GA6qFhiJgtZYrk
9+/mQ6D44fWkpJjWCOP4I12iRa5fr1UyVTslq4D6BmVK44Mhym/kyi9wXkv4fmc=
=j9qu
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
i.MX device tree update for 4.19:
- Add device tree support for i.MX6SLL SoC.
- New board support: ConnectCore 6UL System-On-Module and SBC Express;
ZII SCU2 Mezz, SCU3 ESB, SSMB SPU3 and CFU1 board; i.MX6SLL EVK
board; Engicam i.CoreM6 1.5 Quad/Dual MIPI; LogicPD MX31Lite board;
i.MX53 HSC/DDC boards from K+P.
- Remove fake regulator bus container node and enable USB OTG support
for i.MX6 wandboard and riotboard.
- Populate RAVE SP EEPROM, backlight, power button and watchdog devices
for ZII boards.
- Add cooling-cells for cpufreq cooling device, and add OPP properties
for all CPUs.
- A series from Anson Huang to enable LCD panel and backlight support
for imx6sll-evk board.
- Make pfuze100 sw4 regulator always-on for for a few Freescale/NXP
development boards, because the regulator is critical there and
cannot be turned off.
- Add more device support for i.MX5: AIPSTZ, SAHARA Crypto, M4IF,
Tigerp, PMU, CodaHx4 VPU.
- Enable PMU secure-reg-access for imx51-babbage, imx51-zii-rdu1 and
imx53-ppd board.
- Switch more device tree license to use SPDX identifier.
- Switch to use OF graph to describe the display for imx7d-nitrogen7.
- Add chosen/stdout-path for more boards, so that earlycon can be
enabled more easily on kernel cmdline.
- Convert GPC to new device tree bindings and add Vivante gpu nodes
for i.MX6SL SoC.
- Add more device support for imx6dl-mamoj board: parallel display,
WiFi and USB.
- A series from Stefan Agner to update i.MX6 apalis/colibri boards on
various aspects: SD/MMC card detection, regulators, etc.
* tag 'imx-dt-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (96 commits)
ARM: dts: imx7d: remove "operating-points" property for cpu1
ARM: dts: vf610-zii-ssmb-spu3: Fix W=1 level warnings
ARM: dts: vf610: Add ZII CFU1 board
ARM: dts: imx6dl-mamoj: Add usb host and device support
ARM: dts: imx6dl-mamoj: Add Wifi support
ARM: dts: imx6dl-mamoj: Add parallel display support
ARM: dts: vf610: Add ZII SSMB SPU3 board
ARM: dts: imx6ul-pico-hobbit: Do not hardcode the memory size
ARM: dts: imx6sl-evk: make pfuze100 sw4 always on
ARM: dts: imx6sll-evk: make pfuze100 sw4 always on
ARM: dts: imx6sx-sdb-reva: make pfuze100 sw4 always on
ARM: dts: imx6qdl-sabresd: make pfuze100 sw4 always on
ARM: dts: imx6sl-evk: add missing GPIO iomux setting
ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string
ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config
ARM: dts: imx6sx-nitrogen6sx: remove obsolete display configuration
ARM: dts: imx7d-nitrogen7: use OF graph to describe the display
ARM: dts: imx: Switch Boundary Devices boards to SPDX identifier
ARM: dts: imx6sl: Add vivante gpu nodes
ARM: dts: imx6sll-evk: enable SEIKO 43WVF1G lcdif panel
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- New boards from Laird: WB45N, WB50N, SOM60 modules and DVK, Gatwick
- fix the PMC compatibles
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEXx9Viay1+e7J/aM4AyWl4gNJNJIFAltRmP8ACgkQAyWl4gNJ
NJJpSg/+PCyEw8y05m69iJs2eLnt340MO3Zqdx0FefVkD/BTB4UpZf53h54sfUFR
8Mbrg5QCMpjH/0r/uDfHYiftLn5++UBuCRGSiOqqN9NFuUeraeJpL/VPLtiBgg1E
CpVz7xpIX3vTvH405VEkTXo2lj84Ura7cA+wXovFVk+MrzLb0gkYZ/f0WavjLpmu
cx8SSANj4xbsES8QnkJgOMSxMMY5Ot4QoGjQ6OTMQsK3U0m/axs42BwBW697Ha2A
nKP9wTdfuJjFaIl6MP+ERsDcVXcld++icEHZZYdJl4Vq0a/K0mmn+Cf2kzo/1new
MPU0jSFIC4PYHfihsZhISIk3t5RlPPtR5mKlnBopoBqHJz0pMoRo/Y5RwAnIxBj8
PjmCopiljp7vgecfCjtEWtLhACcVav+ryG+WaYnqtTGOl/qY6YA5BUbHvafTzZmz
9VzCt8d1Offu1GxZ3QtbMXzedwdLIps67roc6xJB5sK/TwbcmehMZy3ktql7M8xm
ImNfagAxHVmlp1FWPFoiyft02sccr5xor/oijIiWwjB+tUO6PqWjZz3vri+mbrEt
Mf1Fw78Upoj5OoyWNize+G9TsSNlg6NBSs5fjQapa7n/Rl/px9hWP4F6VDS4AEnH
85tJZNaXkzsJ2SpGeFvSqUXcZlPTVP8RZ7KITIQsbYRku3vW2s8=
=XVdU
-----END PGP SIGNATURE-----
Merge tag 'at91-ab-4.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/dt
AT91 DT for 4.19:
- New boards from Laird: WB45N, WB50N, SOM60 modules and DVK, Gatwick
- fix the PMC compatibles
* tag 'at91-ab-4.19-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: dts: at91: fix typos for SSC TD functions
ARM: dts: add support for Laird SOM60 module and DVK boards
ARM: dts: add support for Gatwick board based on WB50N
ARM: dts: add support for Laird WB50N cpu module and DVK
ARM: dts: add support for Laird WB45N cpu module and DVK
ARM: dts: at91: add labels to soc dtsi for derivative boards
dt-bindings: add laird and giantec vendor prefix
ARM: dts: fix PMC compatible
ARM: at91: fix USB clock detection handling
dt-bindings: clk: at91: Document all the PMC compatibles
dt-bindings: arm: remove PMC bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing properties (clocks, clock latency) as well to
make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds dts files for two new beaglebone variants for
Octavo Systems OSD3358-SM-RED and Sancloud am335x-sancloud-bbe.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAltQQZkRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMwiw/9Fp6dyretX7g9GQnfXD06/mv+mW1bEimN
Klv87vIiqKqpp8Wn/lokr4K3ajcRpQTkhMuNskKFkAh0tqgNKC4lES7Iw2P6E/dV
V7FRnZwwglCOJayU0zeWHr4cEz0vVFV8huJrC9tm63VAxqHEiqImrhAxZzGoaeFL
C9wv7tcXmcg1gWvpatdRn7mq31LBXCXbWaxmb+HnvxUe8R3+buwWC6XJvHcqO3H8
XmaoMSKeVSW9FASu42S/wTXRgLZwV33gi0yZv/rR8/hkKU/BSb6WwOjrOUXpw16a
ye+seLriNT9WGy1NtrbPYXYGMZj6E9XksDLpg73CLX3nRdYn7fIiasLg+nx+ZAzL
EZfJkQfShLwdoZds1bJr0HUR2k3r1EGEuq0siNRn/8ay8rYzCllM6VtKUhvrx0+t
OeJmpg/tDawLO0SjWTomY3IdzEuheBlRDSV9A3sseXbDo4EeTV9DDRg/uB88WRnX
1Z7nvVfAWo8L1a8dhkaWMet/QkLeAKHAzlGDjG8ccOK62svHgqxWZrTTKEMViNgq
e9/1ayG+HGWI4FFjZ3rLHsFChC8USz/mrYv/PWyIwwF9g7occYQd0MoMmAwzCZ/I
XV9E/Y1RHJJMfq1hJGBH0y9+e6qnrsDDVYA8bpRrTpXwY36ohdNC3EbiOKn8G/uj
rzjBz29zZAo=
=h3F9
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.19/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Few more beaglebone variants for v4.19 merge window
This adds dts files for two new beaglebone variants for
Octavo Systems OSD3358-SM-RED and Sancloud am335x-sancloud-bbe.
* tag 'omap-for-v4.19/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x: add am335x-sancloud-bbe board support
dt-bindings: Add vendor prefix for Sancloud
ARM: dts: Add DT support for Octavo Systems OSD3358-SM-RED based on TI AM335x
Signed-off-by: Olof Johansson <olof@lixom.net>
- A series from Anson Huang to add power management for i.MX6SLL,
including standby and mem mode suspend, cpuidle support, and bus
clock auto gating function, etc.
- A couple of fix-ups on i.MX6SLL cpuidle random build issues.
- A couple of cleanups on stale EPIT timer initialization and RNGA
platform device registration function.
- Configure i.MX51 SoC M4IF to avoid visual artifacts during video
playback.
- Set up i.MX51 and i.MX53 DBGEN bit of ARM_GPC register, so that
clocks within the debug system can be activated.
- Add a Cortex-M4 platform support which will be useful for running
a Linux instance on Cortex-M4 core integrated in i.MX7D SoC.
- Flag of_iomap failure in imx_aips_allow_unprivileged_access()
function by giving a warning in there.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbUeD9AAoJEFBXWFqHsHzO8XQH/jeNhPnOwYa+iAWqTwsdQjka
CY6rfgj/1YQjxlO6uWgbWta+m7D3XxeudCMHFBCGUpcWvEGIR/w/uThQN6N4GlTc
SlXGolvs+kgorCRpIiDb+F5NU8cC6dwdD9qJOCRi5GqN3IlSjs9DnEn8Bm7Bi0qw
mhExhDY/MNMHbUYNTEbig+8pn/74dQfcvKYb2VCnTTIOtJ3PJly3LXSQBJin1yPB
gdMiyl/g348ZO15a02gxyGzDdY9nrYG6erJ4DCxkJhU7cat0TRUFMkON+5KP6DjD
5DWMNtwjfbbjub++jJmp6KO86ZUIPO+H9D1ATOAyqQVm8gxPDBm3fK48OFJycXU=
=owQ6
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
i.MX SoC update for 4.19:
- A series from Anson Huang to add power management for i.MX6SLL,
including standby and mem mode suspend, cpuidle support, and bus
clock auto gating function, etc.
- A couple of fix-ups on i.MX6SLL cpuidle random build issues.
- A couple of cleanups on stale EPIT timer initialization and RNGA
platform device registration function.
- Configure i.MX51 SoC M4IF to avoid visual artifacts during video
playback.
- Set up i.MX51 and i.MX53 DBGEN bit of ARM_GPC register, so that
clocks within the debug system can be activated.
- Add a Cortex-M4 platform support which will be useful for running
a Linux instance on Cortex-M4 core integrated in i.MX7D SoC.
- Flag of_iomap failure in imx_aips_allow_unprivileged_access()
function by giving a warning in there.
* tag 'imx-soc-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: mx5: Set the DBGEN bit in ARM_GPC register
ARM: imx51: Configure M4IF to avoid visual artifacts
ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll
ARM: imx: fix i.MX6SLL build
ARM: imx: flag failure of of_iomap
ARM: i.MX31: remove rnga registration as a platform device
ARM: imx: Provide support for NXP i.MX7D Cortex-M4
ARM: imx: enable bus auto clock gating function for i.mx6sll
ARM: imx: remove i.MX6SLL support in i.MX6SL cpu idle driver
ARM: imx: add cpu idle support for i.MX6SLL
ARM: imx: add L2 page power control for GPC
ARM: imx: add mem mode suspend for i.MX6SLL
ARM: imx: add standby mode suspend for i.MX6SLL
ARM: imx: remove inexistant EPIT timer init
Signed-off-by: Olof Johansson <olof@lixom.net>
* Always enable ARCH_TIMER on SoCs with A7 or A15
All such SoCs have ARCH_TIMER so there is no need for it to be optional.
This allows clean-up which is included in this change.
* Do not compile r8a7779_platform_cpu_kill when it is unused
This avoids a warning by shuffling code into an existing #ifdef
r8a7779 is the R-Car H1 SoC
* Add SMP enabler driver for the RZ/N1D (r9a06g032) SoC
This is to allow SMP to be enabled via DT on the r9a06g032
* Stop compiling headsmp-apmu for non-SMP configs
This is a minor clean-up allowing removal of an #ifdef
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAltRyyUACgkQ189kaWo3
T77hvA//Uw5GUKUsK+ues2P/GlfpDBupmZwg49lU4SzzNh0yUqglAwxha8hkq2/X
JrWzLcOC+4X7vTPpd46Y88G7YjOmcCbExIKFBpicJfPCKRkTe/RguZDp5anS9qGe
oZ/xz3q28pAYxlbfIUXqRmCd15E2gkmku9kYvo0dcFuWziEP9P9CYgRimD0xpXPY
wTGNq0yahOJ7BkxXMXcvpWgIbtRsI5raiSxJiNLver2mTc7O5dxQC3945FlrBdU3
hPlvkvUCHSzN/+G5kIP/gtKPGJ6RgPv5WD+i36qfcpcEJpvWz+Hz74dULzBeCw3H
8p+64xgcmBzPsZcmFRLInFtWFWFjWzTSTYkfSBomwyYlPmq3pq3Ch3tr7epofBF6
S3Oa2iQXhIVkfSwy/qqkYRvgZLsjS+0QfsPuChhIaf4RC1DgTVwlpTk+SPc6gQ3j
nrKsz/rTWFmqYvlZ99JLXM4v16UDEKUE/SgibY7Pk/gM/BhrJbjkPMsNX7P3qHdL
mZmsQSIMspzZP57ShHz04GO2u9XchxagHBrUZ3NXOshNw745N9Wd1bzqvom8nGlR
6sf/MOXsQGS0fTskar5Mm+S7UGBYc0qAEw0SIK4VBq3ruibK5cK7rKxeTKbIuAmD
2b5y0fdqjRGGoOJjp4KBAB5ZZuDpV6PkR3TnBlqSd/ipShC0krs=
=LXu6
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-soc2-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Second Round of Renesas ARM Based SoC Updates for v4.19
* Always enable ARCH_TIMER on SoCs with A7 or A15
All such SoCs have ARCH_TIMER so there is no need for it to be optional.
This allows clean-up which is included in this change.
* Do not compile r8a7779_platform_cpu_kill when it is unused
This avoids a warning by shuffling code into an existing #ifdef
r8a7779 is the R-Car H1 SoC
* Add SMP enabler driver for the RZ/N1D (r9a06g032) SoC
This is to allow SMP to be enabled via DT on the r9a06g032
* Stop compiling headsmp-apmu for non-SMP configs
This is a minor clean-up allowing removal of an #ifdef
* tag 'renesas-arm-soc2-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15
ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill
soc: r9a06g032: don't build SMP files for non-SMP config
ARM: shmobile: Add the R9A06G032 SMP enabler driver
ARM: shmobile: rcar-gen2: Stop compiling headsmp-apmu on !SMP
Signed-off-by: Olof Johansson <olof@lixom.net>
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing property (clock latency) as well to make it all
work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
- check of_iomap and add missing of_node_put since of_find_compatible_node
is invoked on hisilicon SoCs like hip01, hix5hd2 and hi3xxx.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbT1kyAAoJEAvIV27ZiWZcFdcP/2dd0YBj26g6RUf0emNFSATZ
8FOWQEnpq1DsWU/DWmBflhwIfTwHE9xdQfSJzCfgo422RlTM0ZC0dx5LCLDybfK/
Lp5gfxFX0eq4RHKEjZ9+Lf8RFXzkHLM7UiubK1P/MOJOTfCjib/0oLZpDxM3KH+d
GWQirqnLspLvZ62QFGVc6mex7NtxHZBymyItk2MV2hDkwnEqJzloBYKLBRa3zh5I
amzuYQoPC3FAeNuNn1C4xMtBhWYH9FZaC1crnXXWus5KQ+t+3NTViryVWYRN0rjo
nOMfjBYzOx/ZuzRLxSL4fH62hFkUcVy2+B80BVEf5mab/5aKmumk8NegUrpyXTyn
tBNTAkD0guLNYedLE9o7TwE+HVc4EkHh2OCDlSyreF3A8VgYMSVzptlc3bQj90mR
iuvsfNDypvCw85r58R+hKbbXX5VPWUh2P7QabzBlslV5aeQtZfiFuea6zsYeLJez
I5yePdhTv+93iF3Wrt3Nk2TAZtQ1ksjmw06I3vBYxt/q46ZBFo1Ofs3pDynpHULj
ccqA6XbD0a4zKUnzzbg48gWXCqccBSCwZafPpjjelh2ApXO0XuYU9W2Ake8BG/78
0aL+DnU045amlwA1TLW2UtDcGEYecFIhMQ7YNbwpblX6s3YOntfVy27Uv3fLuHkT
Xgl4Yh6wj+NR2+uTI93W
=Qq8S
-----END PGP SIGNATURE-----
Merge tag 'hisi-armv7-soc-for-4.19' of git://github.com/hisilicon/linux-hisi into next/soc
ARM: mach-hisi: Hisilicon SoC updates for 4.19
- check of_iomap and add missing of_node_put since of_find_compatible_node
is invoked on hisilicon SoCs like hip01, hix5hd2 and hi3xxx.
* tag 'hisi-armv7-soc-for-4.19' of git://github.com/hisilicon/linux-hisi:
ARM: hisi: handle of_iomap and fix missing of_node_put
ARM: hisi: check of_iomap and fix missing of_node_put
ARM: hisi: fix error handling and missing of_node_put
Signed-off-by: Olof Johansson <olof@lixom.net>
IPQ8064 and IPQ4019 boards contain NAND flash
memory for which these configs need to be enabled.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Fix all nodes to use proper GIC_* macros for the interrupt type and the
interrupt trigger settings to avoid the boot warnings.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Abhishek Sahu <absahu@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
arm64's new use of KVMs get_events/set_events API calls isn't just
or RAS, it allows an SError that has been made pending by KVM as
part of its device emulation to be migrated.
Wire this up for 32bit too.
We only need to read/write the HCR_VA bit, and check that no esr has
been provided, as we don't yet support VDFSR.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to
their proper location and enable probing using ti-sysc.
In general the first child device address range starts at range 0
from the ti-sysc interconnect target so the move involves adjusting
the child device reg properties for that.
And we cannot yet move mmu_dsp until we have a proper reset controller
driver for rstctrl registers.
In case of any regressions, problem devices can be reverted to probe
with legacy platform data as needed by moving them back and removing
the related interconnect target module node.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Before updating wdt2 to probe with ti-sysc we want to have wdt3
probed with ti-sysc to avoid having them unnecessarily swap order.
With ti-sysc, we probe child devices at module_init time while
and until l4 abe interconnect is converted to use ti-sysc, wdt3
will probe earlier with legacy platform data.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Let's add proper interconnect hierarchy for l4 interconnect
instances with the related ti-sysc interconnect module data as
documented in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping
legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c
files later on in favor of ti-sysc dts data.
For setting up a proper hierarchy for the interconnect and
ti-sysc data, there are multiple reasons:
1. We can use dts ranges to protect registers from being
ioremapped from other devices and prevent hard to track
issues with failed flush of posted write between modules
2. Some of the ranges may not be accessible to operating systems
at all if configured so on high-security devices
3. The interconnect hierarchy provides proper clockdomain
hierarchy that can be used for genpd later on
4. We can avoid almost all deferred probe related issues simply
by probing the resource providing interconnect instance first
for l4 wkup instance
5. With deferred probe issues gone, we can probe everything
later at module_init time except for system timer and interrupt
controller and their clocks.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Each interconnect instance is typically divided into segments
to avoid powering up the whole interconnect. And each segment
has one or more ranges TI specific interconnect target modules
connected to it. Some devices can also have a separate data
access port directly to the parent L3 interconnect for DMA that
can be set up as a separate range.
Note that we cannot yet include this file from omap4.dtsi
until child devices are moved to their proper locations in
the interconnect hierarchy in the following patch. Otherwise
we would have the each module probed twice.
Also note that this does not yet add l4 abe instance, that will
be added separately later on.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add DMATEST support and remove invalid options, such as
CONFIG_BT_HCIUART_H4 is default enabled and CONFIG_SND_SOC_IMX_WM8962
is out of date and not appear in any config file. Please refer to
Documentation/driver-api/dmaengine/dmatest.rst to test MEMCPY feature
of imx-sdma.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Commit b97872d4eb ("ARM: dts: imx: Add missing OPP properties for CPUs")
added "operating-points" property for all CPUs, but i.MX7D already has
"operating-points-v2" property on both CPUs, so no need to add
"operating-points" property again, this patch removes it.
Fixes: b97872d4eb ("ARM: dts: imx: Add missing OPP properties for CPUs")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
- A fix for i.MX6 RDU2 board on the wrong IRQ type of Marvell switch,
which might result in a race condition in the interrupt handler and
cause the OS to miss all future events.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbUVhyAAoJEFBXWFqHsHzOss4H/3nHBKfbjC0twTK3J4ou3jDO
3JboghAt6bxKb/aS1zi8h3d7HDchV5FRkp87TX0qWss6RpS/cMPvQv2DCtgJIYMr
M/M59oxJJsZpen105tMiUFermrPEGz7vmy4FkmG8t2giSQj78XZYQnZsp77AcTyC
IP2wNcVBYwfis3GvDuKgBduZlAV42tqL0U02HsaOvmHjhGcqLzJxlwDAa2es6/zU
KmbBatTR78oP2xf68BXQVB+x8WEjLxNI9J3c4uuLjYTxDxCKU+QNi57XS1VXp13q
72x0lxhe9uTOC+tipvTvj449RigOIfqhlyg7IIE/5xOIKZFUfZZSYZmQ00lx1O4=
=grcI
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-4.18-4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
i.MX fixes for 4.18, round 4:
- A fix for i.MX6 RDU2 board on the wrong IRQ type of Marvell switch,
which might result in a race condition in the interrupt handler and
cause the OS to miss all future events.
* tag 'imx-fixes-4.18-4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx6: RDU2: fix irq type for mv88e6xxx switch
Signed-off-by: Olof Johansson <olof@lixom.net>
R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
Cortex-A15 CPU cores, all of which have ARM architectured timers.
Force use of the ARM architectured timer on these SoCs.
This allows to:
- Remove the calls to shmobile_init_delay() from the corresponding
machine vectors,
- Remove a check in timer setup specific to R-Car Gen2,
- Remove a check in shmobile_init_delay().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
After the cleanup in r8a7779_smp_prepare_cpus(), the only remaining caller of
r8a7779_platform_cpu_kill() is in an ifdef, which leads to a build warning
without CONFIG_HOTPLUG_CPU:
arch/arm/mach-shmobile/smp-r8a7779.c:26:12: error: 'r8a7779_platform_cpu_kill' defined but not used [-Werror=unused-function]
This moves the function inside of that #ifdef to avoid the warning.
Fixes: 62f55ce683 ("ARM: shmobile: r8a7779: Stop powering down secondary CPUs during early boot")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix typo for TD function of pins PIN_PB22 and PIN_PC14
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This adds support for Lairds upcoming SOM module, featuring Marvell WiFi
and Bluetooth, 2Gb NAND / 1Gb LPDDR SDRAM, and an Atmel SAMA5D3 CPU.
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Add support for the LoRa gateway from Laird, the RG1xx.
This board houses the WB50NBT CPU module along with a Semtech SX1301 based
concentrator card.
https://www.lairdtech.com/products/rg1xx-lora-gateway
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This adds support for Lairds CPU module, featuring Atheros wifi, CSR
Bluetooth and, Atmel SAMA5D3 CPU.
https://www.lairdtech.com/products/wb50nbt-wi-fi-bluetooth-module
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This adds support for Lairds combo CPU module, featuring on board
Atheros wifi, CSR Bluetooth radio and, Atmel CPU.
https://www.lairdtech.com/products/wb45nbt
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This adds labels to commonly used device-tree nodes so that derivative
boards can avoid ahb/apb hierarchy.
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Marvell switches report their interrupts in a level sensitive way.
When using edge sensitive detection a race condition in the interrupt
handler of the swich might result in the OS to miss all future events
which might make the switch non-functional.
The problem is that both mv88e6xxx_g2_irq_thread_fn() and
mv88e6xxx_g1_irq_thread_work() sample the irq cause register
(MV88E6XXX_G2_INT_SRC and MV88E6XXX_G1_STS respectively) once and then
handle the observed sources. If after sampling but before all observed
irq sources are handled a new irq source gets active this is not noticed
by the handler which returns unsuspecting, but the interrupt line stays
active which prevents the edge detector to kick in.
All device trees but imx6qdl-zii-rdu2 get this right (most of them by
not specifying an interrupt parent). So fix imx6qdl-zii-rdu2
accordingly.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: f64992d1a9 ("ARM: dts: imx6: RDU2: Add Switch interrupts")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The dts patch for droid4 PWM vibrator has added gpio6 entries to the wrong
node. Let's fix it with a note that there seems to be also other GPIO PWM
issues to fix still to get the PWM vibrator working. So this can wait for
v4.19 merge cycle if necessary.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAltQPwERHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMvERAAqzZoTW6Qd6WnxRQIrIpNHTPpyuiu7uGU
DdaJUvHCn93JfJyuG6VCwSph8SI8o+YVQGV67Rr7TO7GDW8WGrcuMnfB+0z6Xm6Y
HbTlXVP3sImykowoAEFF4VJmSclj5qzYk2n72KlpT7pJQnJqe0DmigCV/IkFn9A6
q1fSKcQH7A0qjPOdefgF/zPVgNbxy1JkO/dzKyXZPc0LmjpwWfNWntbPyqNWi7om
oazVpRwM+8640S7wBhYBn2T0KoQZus8pU/Oy03UAgrUbL4yhcOhZhYJKrmvXmXcW
e/V8k071zrLc9XVL1DYVfFmHA4mzve6efmQnem2krpaki5n6jF5YEkayhiXqC0B2
RF24oKFsuztRTgkkJfGumiuassF3wGdPpAPL2DwFIX5qJwqvcg96AhzdAMc5Af4m
FTFMhtcYgf5G1/yDI8IyVQNoqvBci/n7/zUd7NBluizcZm5YIrcShzAh/WERgxuO
3x+fDhCAP1zzeyFAJlOMhNCYWesRTuT/9kQrP95saXjfcbaXZt8hsARJgXA8x2V/
40ONNcvrAMbC10jqAPzXdTgSdHTFO2cZs3DdCwHSvkFFhfczH/E/2OOKzfxZCxHL
2OCcCOWuZD3WyUlYs01vZOMWPzN/2gJYi4upAMSxyUDN67ios8TKOBM+VU5Ec2Vh
5TqC8lQfmew=
=1jV8
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.18/fixes-rc5-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
One omap dts mismerge fix
The dts patch for droid4 PWM vibrator has added gpio6 entries to the wrong
node. Let's fix it with a note that there seems to be also other GPIO PWM
issues to fix still to get the PWM vibrator working. So this can wait for
v4.19 merge cycle if necessary.
* tag 'omap-for-v4.18/fixes-rc5-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-droid4: fix dts w.r.t. pwm
Signed-off-by: Olof Johansson <olof@lixom.net>
According to the system control bindings, the A3-A4 SRAM node should be
a child node of the SRAM it belongs to. However, it was introduced at the
same level, therefore breaking the binding. Fix this.
Fixes: 8587019625 ("ARM: sun5i: a13: Merge common controllers into the common DTSI")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
address-cells/size-cells is unnecessary for dwmac-sun8i node.
It was in early days, but since a mdio node is used, it could be
removed.
This patch fix the following DT warning:
Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
address-cells/size-cells is unnecessary for dwmac-sun8i node.
It was in early days, but since a mdio node is used, it could be
removed.
This patch fix the following DT warning:
Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
ddress-cells/size-cells is unnecessary for dwmac-sun8i node.
It was in early days, but since a mdio node is used, it could be
removed.
This patch fix the following DT warning:
Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
dts reports incorrect usage of these properties in gpio-keys node.
Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary
The patch is removing these useless properties.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add an LED node, connected to the Processing System (PS)
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Include GPIO dt-bindings and use GPIO_ACTIVE_* constants
to improve readability
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
According to the reference manual, the board has two Micron
MT41K256M16HA-125 DDR3L memory ICs, which have 512 MiB each
Tested on a ZYBO-Z7-20 board
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Both boards are made by Avnet, Inc. So add an additional
value to the compatible property
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a dts for MYIR Z-turn board and respective target in Makefile.
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds parallel display support for i.MX6DL Mamoj board
along with relevant backlight through pwm.
LCD power sequence is added by 'Michael Trimarchi'.
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Since commit ce99d0bf31 ("kbuild: clear LDFLAGS in the top Makefile"),
the top-level Makefile caters to this.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
- add NAND controller on multi_v7
- add SFP support on mvebu_v7
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCW09bkAAKCRALBhiOFHI7
1RYzAJ4vD274nhcu4Qt3n2vOzS5Wae+sMQCeNmutPbYM9fJg5A3KH/7jxJ0yeyM=
=K1xh
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig-4.19-1' of git://git.infradead.org/linux-mvebu into next/defconfig
mvebu defconfig for 4.19 (part 1)
- add NAND controller on multi_v7
- add SFP support on mvebu_v7
* tag 'mvebu-defconfig-4.19-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu_v7_defconfig: enable SFP support
ARM: mvebu_v7_defconfig: sync defconfig
ARM: multi_v7_defconfig: Add Marvell NAND controller support
Signed-off-by: Olof Johansson <olof@lixom.net>
- remove potential call from invalid context in boot_secondary
- allow using CONFIG_FORTIFY_SOURCE in pmsu.c
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCW09bLwAKCRALBhiOFHI7
1SIJAJ9VODAIlUU46uOxaQOD1i+RNRRA2gCbBF+P1oRU8OZllnfVwBhgQS0hY/4=
=6j8Z
-----END PGP SIGNATURE-----
Merge tag 'mvebu-arm-4.19-1' of git://git.infradead.org/linux-mvebu into next/soc
mvebu arm for 4.19 (part 1)
- remove potential call from invalid context in boot_secondary
- allow using CONFIG_FORTIFY_SOURCE in pmsu.c
* tag 'mvebu-arm-4.19-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: convert secondary CPU clock sync to hotplug state
ARM: mvebu: declare asm symbols as character arrays in pmsu.c
Signed-off-by: Olof Johansson <olof@lixom.net>
This enables support for SFP cages on SolidRun Armada 38x platforms.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Use savedefconfig to sync defconfig for current kernel. No change in
generated configuration.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
- the pxa architecture is ported to dma slavemap
- some minor AC97 fixes
- some minor board fixes
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEExgkueSa0u8n4Ls+HA/Z63R24yxIFAltM+OUXHHJvYmVydC5q
YXJ6bWlrQGZyZWUuZnIACgkQA/Z63R24yxJZmw/8Cg/SXNLgShgoHAhDBth/pOc7
rq4iZwRFi4d2SQowQAj+booRrEuUePnvnpjbPby4eY/nNsfEC+KsZLDJcdVjeqsN
HG+V/0SQ6tTFzCfDLR9DS75DEyCQY5kjJmAhcWRQV2QKLbXHP2tnRbqvwNS++ltT
xZaKwULvC6uVw8DveVyBmWz5aXCSwF9LjFdY2FY1fnfSd76phtjuaLiVF9akH+6C
x8D+piuloMhxM8w3rX3jZu3RO/gaG+57gYBaVNM0soHXz73zRnf/qvn4bbNmcLaK
K2m5slB+S5/QFLWBZG4uZFRF0eZ2aUtNLGjRsT3HFfP6iitc35FAIhdj76vvTk4U
XDoD89Sjzi/jprvlnHkJESt16PZUP1F2jbrS8aTE7Ma9OMv0BogWMebEcJ0TpzU2
d5SCvGdD+ZOhwUTrmPdLSYjnAjjJqxQMT9TAtA7oYCWJs9aEiIp02mxXQx6ddRCH
6C5KOY8qC03x6kWqy1lEb7ySbwldcHprf1ZGvVI1VizDdWkjblhdvstJW10elIfd
7lnUmyE0Dy7AsJclR91NEfE1p+w6HZ9z8SP9EH5/54g2/pLr8KEsEvXkPBks0Twj
znDFx3ystqK26XHme8LBxtnQbY+ghl5XdERbeVHFBourCdjKol94asa6Yk9yET1h
s31jjWQ1+ib9XokiWJY=
=dvhR
-----END PGP SIGNATURE-----
Merge tag 'pxa-for-4.19-v2' of https://github.com/rjarzmik/linux into next/soc
This is the pxa changes for 4.19 cycle :
- the pxa architecture is ported to dma slavemap
- some minor AC97 fixes
- some minor board fixes
* tag 'pxa-for-4.19-v2' of https://github.com/rjarzmik/linux:
net: smc91x: remove the dmaengine compat need
net: smc911x: remove the dmaengine compat need
ARM: pxa: zylonite: use the new ac97 bus support
ARM: pxa: add the missing AC97 clocks
ARM: pxa: mioa701 convert to the new AC97 bus
ARM: pxa: hx4700: fix the usb client
ARM: pxa: change SSP DMA channels allocation
ARM: pxa: remove the DMA IO resources
dmaengine: pxa: document pxad_param
ata: pata_pxa: remove the dmaengine compat need
mtd: rawnand: marvell: remove the dmaengine compat need
media: pxa_camera: remove the dmaengine compat need
mmc: pxamci: remove the dmaengine compat need
dmaengine: pxa: add a default requestor policy
ARM: pxa: add dma slave map
dmaengine: pxa: use a dma slave map
Signed-off-by: Olof Johansson <olof@lixom.net>
Now that the vhub driver is upstream and the device-trees
updated, let's enable this by default.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Now that the vhub driver is upstream and the device-trees
updated, let's enable this by default.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The aspeed pwm driver always sets the clock source to 24MHz, specify
the fixed clock in device tree to make sure the driver is using the
correct clock frequency to calculate the fan speed.
Signed-off-by: Lei YU <mine260309@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
None of the board files are overloading those hooks, so let's drop them
from struct platform_nand_ctrl.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This adds the Ethernet and Realtek switch device to the
D-Link DIR-685 Gemini-based device.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Since for ULP1 PM mode of SAMA5D2 the wakeup sources are limited and
well known add a method to check if these wakeup sources are defined by
user (either via DT or filesystem). In case there are no wakeup sources
defined for ULP1 the PM suspend will fail, otherwise these will be
configured in fast startup registers of PMC. Since wakeup sources of
ULP1 need also to be configured in SHDWC registers the code was a bit
changed to map the SHDWC also in case ULP1 is requested by user (this
was done in the initialization phase). In case the ULP1 initialization
fails the ULP0 mode is used (this mode was also used in case backup mode
initialization failed).
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
In the ULP1 mode, in order to achieve the lowest power consumption
with the system in retention mode and be able to resume on the wake
up events, all the clocks are shut off, inclusive the embedded 12MHz
RC oscillator, and the number of wake up sources is limited as well.
When the wake up event is asserted, the embedded 12MHz RC oscillator
restarts automatically.
The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.
The previous size of pm_suspend.o was 2148 bytes. With the addition of
ULP1 mode the new size of pm_suspend.o raised at 2456 bytes.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[claudiu.beznea@microchip.com: aligned with 4.18-rc1]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Switch to use ULP0 naming instead of slow clock naming for power modes, to
be as closed as possible to datasheet. This commit does the necessary
renaming and macro addition to be as close as possible to the namings
from [1].
[1] https://lore.kernel.org/lkml/1470650705-31418-3-git-send-email-wenyou.yang@atmel.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The "Beaglebone Enhanced" by Sancloud is based on the Beaglebone Black,
but with the following differences:
* Gigabit capable PHY
* Extra USB hub, optional i2c control
* lps3331ap barometer connected over i2c
* MPU6050 6 axis MEMS accelerometer/gyro connected over i2c
* 1GiB DDR3 RAM
* RTL8723 Wifi/Bluetooth connected over USB
Tested on a revision G board.
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There are two variants of imx6ul-pico boards: one with 256MB and
another one with 512MB of RAM.
Do not hardcode the memory size in the device tree and let the
bootloader fill the correct value instead.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SL EVK board, pfuze100 sw4 supplies
LPDDR2 which is critical for system, must be
always on.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SLL EVK board, pfuze100 sw4 supplies
LPDDR3 which is critical for system, must be
always on.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SX SDB Rev-A board, pfuze100 sw4 supplies
csi, audio codec and i2c etc., these modules do NOT
implement power domain control, so pfuze100 sw4
needs to be always on to make sure these modules
work normally.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6QDL Sabre-SD board, pfuze100 sw4 supplies
GPS, touch and RGMII etc., these modules do NOT
implement power domain control, so pfuze100 sw4
needs to be always on to make sure these modules
work normally.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
OSD3358-SM-RED is a dev board for OSD335x System-in-Package(SiP) devices from
Octavo Systems.
This board family can be indentified by the A335BNLTOS00 in the at24 eeprom:
A2: [aa 55 33 ee 41 33 33 35 42 4e 4c 54 4f 53 30 30 |.U3.A335BNLTOS00|]
https://octavosystems.com/octavo_products/osd3358-sm-red/
Signed-off-by: Neeraj Dantu <neeraj.dantu@octavosystems.com>
CC: Tony Lindgren <tony@atomide.com>
CC: Robert Nelson <robertcnelson@gmail.com>
CC: Jason Kridner <jkridner@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On i.MX6SL EVK board, the MX6SL_PAD_KEY_ROW5 pin is
used as lcd 3v3 regulator control pin, need to make
sure MX6SL_PAD_KEY_ROW5 is muxed as GPIO function
for controlling lcd 3v3 regulator.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by; Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
It looks like I made a nasty typo in the original patch which resulted
in missing watchdog device. Fix it.
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: cphealy@gmail.com
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Instead of relying on default values, configure PAD_AUD3_BB_CK to be a
GPIO explicitly. While at, it change the pad configuration to enable
a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH).
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: cphealy@gmail.com
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
pwm node should not be under gpio6 node in the device tree.
This fixes detection of the pwm on Droid 4.
Fixes: 6d7bdd328d ("ARM: dts: omap4-droid4: update touchscreen")
Signed-off-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
[tony@atomide.com: added fixes tag]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This display configuration isn't working as-is as it depends on the
tfp410 LCD to HDMI bridge. This will need to be updated later once
the DRM MXSFB driver will be the default.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
To make use of the new eLCDIF DRM driver OF graph description is
required. Describe the display using OF graph nodes.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The imx6sl soc has gpu_2d and gpu_vg, no 3d support:
etnaviv-gpu 2200000.gpu: model: GC320, revision: 5007
etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215
The IP blocks seem to be already supported.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX6SLL EVK board, lcd regulator is controlled
by GPIO4 IO03 using MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 pin,
NOT MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08, correct it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add 'secure-reg-access' property to enable PMU and hardware counters
so that they can be properly used with the 'perf' tool.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add 'secure-reg-access' property to enable PMU and hardware counters
so that they can be properly used with the 'perf' tool.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add 'secure-reg-access' property to enable PMU and hardware counters
so that they can be properly used with the 'perf' tool.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
[fabio: kept the change only in imx53-ppd context]
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Use the the DRM driver for MXSFB LCD controller (used in i.MX23/
i.MX28/i.MX6SX or i.MX7). Remove CONFIG_FB_MXS which will soon be
removed.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Use the the DRM driver for MXSFB LCD controller (used in i.MX23/
i.MX28/i.MX6SX or i.MX7). Remove CONFIG_FB_MXS which will soon be
removed.
Note that this does not remove CONFIG_FB. CONFIG_FB gets selected
implicity by CONFIG_DRM/CONFIG_DRM_KMS_FB_HELPER.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The ConnectCore 6UL Single Board Computer (SBC) Express contains the
ConnectCore 6UL System-On-Module.
Its hardware specifications are:
* 256MB DDR3 memory
* 256MB NAND flash
* Single Ethernet
* USB Host and USB-OTG
* MicroSD external storage
* Groove connectors and Raspberry Pi Hat compatible expansion header
Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The ConnectCore 6UL System-On-Module has the following hardware
specification:
* Based on a NXP i.MX6UL SoC
* Industrial temperature ranges (-40ºC to +85ºC)
* Up to 1GB DDR3 memory
* Up to 2GB NAND flash
* Dual Ethernet
* On module 802.11 WiFi and Bluetooth 4.2 (QCA6564)
* On module NXP Kinetis KL03
* On module Microchip ATECC508A crypto element
Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx51-zii-rdu1 has an external watchdog in the environment
microcontroller, so disable the internal one.
This aligns with what was done in commit 7055f71403 ("ARM: dts:
imx6: RDU2: disable internal watchdog") for imx6 rdu2 board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Relying on an unchecked of_iomap() which can return NULL is problematic
here, an explicit check seems mandatory. Also the call to
of_find_compatible_node() returns a device node with refcount incremented
therefor an explicit of_node_put() is needed here.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Fixes: commit 22bae42904 ("ARM: hi3xxx: add hotplug support")
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
of_find_compatible_node() returns a device node with refcount incremented
and thus needs an explicit of_node_put(). Further relying on an unchecked
of_iomap() which can return NULL is problematic here, after all ctrl_base
is critical enough for hix5hd2_set_cpu() to call BUG() if not available
so a check seems mandated here.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
0002 Fixes: commit 06cc5c1d4d ("ARM: hisi: enable hix5hd2 SoC")
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
of_iomap() can return NULL which seems critical here and thus should be
explicitly flagged so that the cause of system halting can be understood.
As of_find_compatible_node() is returning a device node with refcount
incremented it must be explicitly decremented here.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Fixes: commit 7fda91e731 ("ARM: hisi: enable smp for HiP01")
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Normally, we didn't release this kind of baord to user. This specific
board exists only in the early stage of development inside MediaTek -
and that may confuse peoples.
Hence this patch removes related files accordingly.
Cc: John Crispin <john@phrozen.org>
Cc: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The reserved memory for the VGA frame buffer is at the wrong address
for this system.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This is an eval board, it makes sense to enable many
functions by default. This changes the device-tree to
set port A to be a USB device and leave port B as a
host, along with a little comment explaining how to
change it.
(the vhub device can only exist on port A on this SoC)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This adds the (disabled by default) device node for the
Aspeed virtual hub,a long with clocks and pinmux.
This also adds the missing pinmux definition for it
(the kernel driver already knows about it).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This adds the (disabled by default) device node for the
Aspeed virtual hub,a long with clocks and pinmux.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Set the default pinmux for EHCIs so boards don't have to do
it an document why it is not set for UHCI.
Remove the properties from the AST2500 EVB board which are
now redundant
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Set the default pinmux for EHCI so boards don't have to do
it, and document why it is not set for UHCI.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Pio-leds (near GPIO-Header) are swapped and LOW-active.
This patch restores the expected behaviour.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Instead of setting the DMA ops pointer to NULL, set the correct,
non-IOMMU ops depending on the device's coherency setting.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
- A fix for OMAP5 and DRA7 to make the branch predictor hardening
settings take proper effect on secondary cores
- Disable USB OTG on am3517 since current driver isn't working
- Fix thermal sensor register settings on Armada 38x
- Fix suspend/resume IRQs on pxa3xx
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAltK4qkPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3pS0P/i4cTb8pESaYltSiVXePn8Ii6LJa0zxKZ4SK
Yb2jBAFliG319HX2uFNsu42DfhgfdjBlhjkK/5pyOmMyo/t6YLDmC+qmeMhSCwbi
913eZav3UxdegJWFauU8P/khyxPD2nCeDqETzhANuzEB6+ayhi+cgIjpnx+8JLyK
0q5cifBEdRbZO9UGG+IFqt3TLpeAuCIbWLzTCOmdEQ706Zw2TPzzR6RTBt+kfupA
j7Z0pg1yzK40TWyv1ZOyYC7yw2S+9cuT4gdXE/DUgyT4dGlE/deE9iT9D/s8fgAL
Fser9jLbC5rbNQ1MnLRuGtbidvpiq2iCyf7G/FTJD3eoe1AGeaVooa+Jsz9LgEN6
JFJ/sxD8c6PSAJ8t9Dmv9eFOhia0V8XzjtEinWJ2E8F0cgMLxG1y4Ek0cnvaRgZG
2VMfNLIN0iQvYj1FHLJEYkOFEJ+3szJYC8Ejr5RdMUAShUHzqTw1XB4D9IPljJm9
fvrk20LmHRosvcrtqgUNRtMdfEvnTaUMB427ywYyH6Mz75L30CyE7FWohtoL+Qm3
mjB/qQ+c4dWj0YHKLSRhG40hP4Bzo/ljeuzgLs3/crRh12qBHxhE73rUvCpctCyA
VBrU4F+I/a8cJPDqLYtwK8RuMFcYQTWogF3OVWIa+xlWRINYFO8hTgHETSHUtkQY
TGpglcH0
=lmky
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
- A fix for OMAP5 and DRA7 to make the branch predictor hardening
settings take proper effect on secondary cores
- Disable USB OTG on am3517 since current driver isn't working
- Fix thermal sensor register settings on Armada 38x
- Fix suspend/resume IRQs on pxa3xx
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: am3517.dtsi: Disable reference to OMAP3 OTG controller
ARM: DRA7/OMAP5: Enable ACTLR[0] (Enable invalidates of BTB) for secondary cores
ARM: pxa: irq: fix handling of ICMR registers in suspend/resume
ARM: dts: armada-38x: use the new thermal binding
- Add Vitesse switch chips
- Add a new DT for a reference design
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJbSoLtAAoJEEEQszewGV1zjT4P/1FmTC1IwCg0omGmBqhdeUyP
NNgqdPU3vKxNwA4AiaNXedUUgIm/zP1AO/LwsZp+2/e7i0yi54XRJY4eKcLRUq9O
oP0AEG1fIDulKfCJhnh35vSJUpSAKoR2yiWmZCsHfRIiTs73L00cTJebJHtgF7TX
gC4og0DAWZ4iL6A4nVqoV7pQf52io1fZntAdu7+y2qxtVZ8lytJAgZM6m+z3R42S
cW5PAD9a0VAc1/tQambpHqblgw6lMcDbnrd141L1vG7v037gjr15sFnoYQ+vXWle
gQS1b6dbOpFuF/S6+tuitH1YM5yqhQPxR6myoJdmi2J3bY9jtD3uEOuVWHMPt1d7
Dqd+9hjtCK8MQy6BXq8UbFcAPltvp1Qqr59FT9UOqcgkBKpNleBigViRbjt4btzd
VBmEOkHBHia/BiyxnSf6QMpVIMziWaGRcL2AUO8hxprZqZT6ls9LIWeCDV+cKUuT
SY9tm+NrZ4j1p81CVDVr+jl/mNyfMuFM7gth/4uWDuEhs4Lz1TcxumQHfZ6byYz4
XhpydQKGholUxMJAMihIBdJYWz8s6lm/XiXvYE7Wpexe654xY1uhhEsFXDjrf1Fq
avBAizDRb9tZVRtColmZKuxilKq8CgJw3EaLPG7c53bNbmeAq6txl6jFG0aUdCZV
5LqtekLlzAceF9MlaXEY
=3RrW
-----END PGP SIGNATURE-----
Merge tag 'gemini-dts-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
Gemini DTS updates for v4.19:
- Add Vitesse switch chips
- Add a new DT for a reference design
* tag 'gemini-dts-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: Add devicetree for Storlink/Storm SL93512R
ARM: dts: Add Vitesse G5e switch to the Gemini SQ201
ARM: dts: Add WAN ethernet port to the SQ201
Signed-off-by: Olof Johansson <olof@lixom.net>
The Storlink Gemini324 EV-Board also known as Storm
Semiconductor SL93512R_BRD is ground zero for the Gemini
devices. We add a device tree so we can support it, it
turns out to be pretty trivial.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the Vitesse G5e ethernet switch to the Square
One Itian SQ201 router device tree.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This sets up the ethernet interface and PHY for the
WAN ethernet port which uses a Marvell PHY.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
