There is a DWC2 USB core in these SoCs. To make USB work we need to first
reset and power the state machine. These are SoC specific registers and
not part of the actual USB core.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11449/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
request_mem_region() returns a pointer and not an integer with an error
value. A check for "< 0" on a pointer will cause problems, replace it
with not null checks instead. This was found with sparse.
Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11395/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A reboot sometimes lead to a none working phy. An explicit reboot fixes the
problem.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8044/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add a reset-controller binding for the reset registers found on the lantiq
SoC.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8043/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Explicitly enable the clock gate of the internal GPHYs found on xrx200.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to
boot them up.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4522
The XRX200 SoC family has a different register layout for reading the boot
selection bits.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4519
Panic() invokes printk() to add a \n internally, so panic arguments should
not themselves end in \n. Panic invocations in arch/mips and elsewhere
are inconsistently sometimes terminating in \n, sometimes not.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The code located at arch/mips/lantiq/ included module.h to be able to use
the EXPORT_SYMBOL* macros. These can now be directly included using
export.h.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add support for the Lantiq XWAY family of Mips24KEc SoCs.
* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)
The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.
The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function
int lq_gpio_request(unsigned int pin, unsigned int alt0,
unsigned int alt1, unsigned int dir, const char *name);
which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.
The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
