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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 12:06:53 +07:00
octeontx2-af: NIX AQ instruction enqueue support
Add support for a RVU PF/VF to submit instructions to NIX AQ via mbox. Instructions can be to init/write/read RQ/SQ/CQ/RSS contexts. In case of read, context will be returned as part of response to the mbox msg received. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
709a4f0c25
commit
ffb0abd7e9
@ -149,7 +149,8 @@ M(NPA_HWCTX_DISABLE, 0x403, hwctx_disable_req, msg_rsp) \
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/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
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/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
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M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc_req, nix_lf_alloc_rsp) \
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M(NIX_LF_FREE, 0x8001, msg_req, msg_rsp)
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M(NIX_LF_FREE, 0x8001, msg_req, msg_rsp) \
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M(NIX_AQ_ENQ, 0x8002, nix_aq_enq_req, nix_aq_enq_rsp)
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/* Messages initiated by AF (range 0xC00 - 0xDFF) */
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#define MBOX_UP_CGX_MESSAGES \
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@ -379,4 +380,37 @@ struct nix_lf_alloc_rsp {
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u8 mac_addr[ETH_ALEN];
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};
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/* NIX AQ enqueue msg */
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struct nix_aq_enq_req {
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struct mbox_msghdr hdr;
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u32 qidx;
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u8 ctype;
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u8 op;
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union {
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struct nix_rq_ctx_s rq;
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struct nix_sq_ctx_s sq;
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struct nix_cq_ctx_s cq;
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struct nix_rsse_s rss;
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struct nix_rx_mce_s mce;
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};
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union {
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struct nix_rq_ctx_s rq_mask;
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struct nix_sq_ctx_s sq_mask;
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struct nix_cq_ctx_s cq_mask;
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struct nix_rsse_s rss_mask;
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struct nix_rx_mce_s mce_mask;
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};
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};
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struct nix_aq_enq_rsp {
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struct mbox_msghdr hdr;
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union {
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struct nix_rq_ctx_s rq;
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struct nix_sq_ctx_s sq;
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struct nix_cq_ctx_s cq;
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struct nix_rsse_s rss;
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struct nix_rx_mce_s mce;
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};
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};
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#endif /* MBOX_H */
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@ -261,4 +261,7 @@ int rvu_mbox_handler_NIX_LF_ALLOC(struct rvu *rvu,
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struct nix_lf_alloc_rsp *rsp);
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int rvu_mbox_handler_NIX_LF_FREE(struct rvu *rvu, struct msg_req *req,
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struct msg_rsp *rsp);
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int rvu_mbox_handler_NIX_AQ_ENQ(struct rvu *rvu,
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struct nix_aq_enq_req *req,
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struct nix_aq_enq_rsp *rsp);
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#endif /* RVU_H */
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@ -16,6 +16,38 @@
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#include "rvu.h"
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#include "cgx.h"
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static inline struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)
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{
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if (blkaddr == BLKADDR_NIX0 && hw->nix0)
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return hw->nix0;
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return NULL;
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}
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static bool is_valid_txschq(struct rvu *rvu, int blkaddr,
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int lvl, u16 pcifunc, u16 schq)
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{
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struct nix_txsch *txsch;
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struct nix_hw *nix_hw;
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nix_hw = get_nix_hw(rvu->hw, blkaddr);
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if (!nix_hw)
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return false;
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txsch = &nix_hw->txsch[lvl];
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/* Check out of bounds */
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if (schq >= txsch->schq.max)
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return false;
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spin_lock(&rvu->rsrc_lock);
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if (txsch->pfvf_map[schq] != pcifunc) {
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spin_unlock(&rvu->rsrc_lock);
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return false;
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}
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spin_unlock(&rvu->rsrc_lock);
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return true;
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}
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static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
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u64 format, bool v4, u64 *fidx)
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{
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@ -159,6 +191,198 @@ static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr,
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return 0;
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}
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static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
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struct nix_aq_inst_s *inst)
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{
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struct admin_queue *aq = block->aq;
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struct nix_aq_res_s *result;
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int timeout = 1000;
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u64 reg, head;
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result = (struct nix_aq_res_s *)aq->res->base;
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/* Get current head pointer where to append this instruction */
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reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS);
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head = (reg >> 4) & AQ_PTR_MASK;
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memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)),
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(void *)inst, aq->inst->entry_sz);
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memset(result, 0, sizeof(*result));
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/* sync into memory */
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wmb();
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/* Ring the doorbell and wait for result */
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rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1);
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while (result->compcode == NIX_AQ_COMP_NOTDONE) {
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cpu_relax();
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udelay(1);
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timeout--;
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if (!timeout)
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return -EBUSY;
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}
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if (result->compcode != NIX_AQ_COMP_GOOD)
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/* TODO: Replace this with some error code */
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return -EBUSY;
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return 0;
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}
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static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req,
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struct nix_aq_enq_rsp *rsp)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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u16 pcifunc = req->hdr.pcifunc;
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int nixlf, blkaddr, rc = 0;
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struct nix_aq_inst_s inst;
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struct rvu_block *block;
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struct admin_queue *aq;
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struct rvu_pfvf *pfvf;
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void *ctx, *mask;
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u64 cfg;
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pfvf = rvu_get_pfvf(rvu, pcifunc);
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
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if (!pfvf->nixlf || blkaddr < 0)
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return NIX_AF_ERR_AF_LF_INVALID;
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block = &hw->block[blkaddr];
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aq = block->aq;
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if (!aq) {
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dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__);
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return NIX_AF_ERR_AQ_ENQUEUE;
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}
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nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
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if (nixlf < 0)
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return NIX_AF_ERR_AF_LF_INVALID;
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switch (req->ctype) {
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case NIX_AQ_CTYPE_RQ:
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/* Check if index exceeds max no of queues */
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if (!pfvf->rq_ctx || req->qidx >= pfvf->rq_ctx->qsize)
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rc = NIX_AF_ERR_AQ_ENQUEUE;
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break;
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case NIX_AQ_CTYPE_SQ:
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if (!pfvf->sq_ctx || req->qidx >= pfvf->sq_ctx->qsize)
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rc = NIX_AF_ERR_AQ_ENQUEUE;
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break;
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case NIX_AQ_CTYPE_CQ:
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if (!pfvf->cq_ctx || req->qidx >= pfvf->cq_ctx->qsize)
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rc = NIX_AF_ERR_AQ_ENQUEUE;
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break;
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case NIX_AQ_CTYPE_RSS:
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/* Check if RSS is enabled and qidx is within range */
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cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf));
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if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx ||
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(req->qidx >= (256UL << (cfg & 0xF))))
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rc = NIX_AF_ERR_AQ_ENQUEUE;
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break;
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default:
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rc = NIX_AF_ERR_AQ_ENQUEUE;
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}
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if (rc)
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return rc;
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/* Check if SQ pointed SMQ belongs to this PF/VF or not */
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if (req->ctype == NIX_AQ_CTYPE_SQ &&
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req->op != NIX_AQ_INSTOP_WRITE) {
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if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ,
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pcifunc, req->sq.smq))
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return NIX_AF_ERR_AQ_ENQUEUE;
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}
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memset(&inst, 0, sizeof(struct nix_aq_inst_s));
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inst.lf = nixlf;
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inst.cindex = req->qidx;
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inst.ctype = req->ctype;
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inst.op = req->op;
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/* Currently we are not supporting enqueuing multiple instructions,
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* so always choose first entry in result memory.
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*/
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inst.res_addr = (u64)aq->res->iova;
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/* Clean result + context memory */
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memset(aq->res->base, 0, aq->res->entry_sz);
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/* Context needs to be written at RES_ADDR + 128 */
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ctx = aq->res->base + 128;
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/* Mask needs to be written at RES_ADDR + 256 */
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mask = aq->res->base + 256;
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switch (req->op) {
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case NIX_AQ_INSTOP_WRITE:
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if (req->ctype == NIX_AQ_CTYPE_RQ)
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memcpy(mask, &req->rq_mask,
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sizeof(struct nix_rq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_SQ)
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memcpy(mask, &req->sq_mask,
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sizeof(struct nix_sq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_CQ)
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memcpy(mask, &req->cq_mask,
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sizeof(struct nix_cq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_RSS)
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memcpy(mask, &req->rss_mask,
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sizeof(struct nix_rsse_s));
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/* Fall through */
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case NIX_AQ_INSTOP_INIT:
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if (req->ctype == NIX_AQ_CTYPE_RQ)
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memcpy(ctx, &req->rq, sizeof(struct nix_rq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_SQ)
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memcpy(ctx, &req->sq, sizeof(struct nix_sq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_CQ)
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memcpy(ctx, &req->cq, sizeof(struct nix_cq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_RSS)
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memcpy(ctx, &req->rss, sizeof(struct nix_rsse_s));
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break;
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case NIX_AQ_INSTOP_NOP:
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case NIX_AQ_INSTOP_READ:
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case NIX_AQ_INSTOP_LOCK:
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case NIX_AQ_INSTOP_UNLOCK:
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break;
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default:
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rc = NIX_AF_ERR_AQ_ENQUEUE;
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return rc;
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}
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spin_lock(&aq->lock);
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/* Submit the instruction to AQ */
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rc = nix_aq_enqueue_wait(rvu, block, &inst);
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if (rc) {
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spin_unlock(&aq->lock);
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return rc;
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}
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if (rsp) {
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/* Copy read context into mailbox */
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if (req->op == NIX_AQ_INSTOP_READ && !rc) {
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if (req->ctype == NIX_AQ_CTYPE_RQ)
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memcpy(&rsp->rq, ctx,
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sizeof(struct nix_rq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_SQ)
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memcpy(&rsp->sq, ctx,
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sizeof(struct nix_sq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_CQ)
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memcpy(&rsp->cq, ctx,
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sizeof(struct nix_cq_ctx_s));
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else if (req->ctype == NIX_AQ_CTYPE_RSS)
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memcpy(&rsp->rss, ctx,
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sizeof(struct nix_cq_ctx_s));
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}
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}
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spin_unlock(&aq->lock);
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return rc;
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}
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int rvu_mbox_handler_NIX_AQ_ENQ(struct rvu *rvu,
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struct nix_aq_enq_req *req,
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struct nix_aq_enq_rsp *rsp)
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{
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return rvu_nix_aq_enq_inst(rvu, req, rsp);
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}
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int rvu_mbox_handler_NIX_LF_ALLOC(struct rvu *rvu,
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struct nix_lf_alloc_req *req,
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struct nix_lf_alloc_rsp *rsp)
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@ -346,14 +570,6 @@ int rvu_mbox_handler_NIX_LF_FREE(struct rvu *rvu, struct msg_req *req,
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return 0;
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}
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static inline struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)
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{
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if (blkaddr == BLKADDR_NIX0 && hw->nix0)
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return hw->nix0;
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return NULL;
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}
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static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
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{
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struct nix_txsch *txsch;
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@ -426,6 +426,424 @@ struct nix_aq_res_s {
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u64 reserved_64_127; /* W1 */
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};
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/* NIX Completion queue context structure */
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struct nix_cq_ctx_s {
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u64 base;
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#if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
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u64 wrptr : 20;
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u64 avg_con : 9;
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u64 cint_idx : 7;
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u64 cq_err : 1;
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u64 qint_idx : 7;
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u64 rsvd_81_83 : 3;
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u64 bpid : 9;
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u64 rsvd_69_71 : 3;
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u64 bp_ena : 1;
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u64 rsvd_64_67 : 4;
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#else
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u64 rsvd_64_67 : 4;
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u64 bp_ena : 1;
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u64 rsvd_69_71 : 3;
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u64 bpid : 9;
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u64 rsvd_81_83 : 3;
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u64 qint_idx : 7;
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u64 cq_err : 1;
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u64 cint_idx : 7;
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u64 avg_con : 9;
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u64 wrptr : 20;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
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u64 update_time : 16;
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u64 avg_level : 8;
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u64 head : 20;
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u64 tail : 20;
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#else
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u64 tail : 20;
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u64 head : 20;
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u64 avg_level : 8;
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u64 update_time : 16;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
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u64 cq_err_int_ena : 8;
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u64 cq_err_int : 8;
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u64 qsize : 4;
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u64 rsvd_233_235 : 3;
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u64 caching : 1;
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u64 substream : 20;
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u64 rsvd_210_211 : 2;
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u64 ena : 1;
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u64 drop_ena : 1;
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u64 drop : 8;
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u64 dp : 8;
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#else
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u64 dp : 8;
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u64 drop : 8;
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u64 drop_ena : 1;
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u64 ena : 1;
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u64 rsvd_210_211 : 2;
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u64 substream : 20;
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u64 caching : 1;
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u64 rsvd_233_235 : 3;
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u64 qsize : 4;
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u64 cq_err_int : 8;
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u64 cq_err_int_ena : 8;
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#endif
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};
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/* NIX Receive queue context structure */
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struct nix_rq_ctx_s {
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#if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
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u64 wqe_aura : 20;
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u64 substream : 20;
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u64 cq : 20;
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u64 ena_wqwd : 1;
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u64 ipsech_ena : 1;
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u64 sso_ena : 1;
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u64 ena : 1;
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#else
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u64 ena : 1;
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u64 sso_ena : 1;
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u64 ipsech_ena : 1;
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u64 ena_wqwd : 1;
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u64 cq : 20;
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u64 substream : 20;
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u64 wqe_aura : 20;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
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u64 rsvd_127_122 : 6;
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u64 lpb_drop_ena : 1;
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u64 spb_drop_ena : 1;
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u64 xqe_drop_ena : 1;
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u64 wqe_caching : 1;
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u64 pb_caching : 2;
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u64 sso_tt : 2;
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u64 sso_grp : 10;
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u64 lpb_aura : 20;
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u64 spb_aura : 20;
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#else
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u64 spb_aura : 20;
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u64 lpb_aura : 20;
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u64 sso_grp : 10;
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u64 sso_tt : 2;
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u64 pb_caching : 2;
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u64 wqe_caching : 1;
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u64 xqe_drop_ena : 1;
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u64 spb_drop_ena : 1;
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u64 lpb_drop_ena : 1;
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u64 rsvd_127_122 : 6;
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#endif
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#if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
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u64 xqe_hdr_split : 1;
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u64 xqe_imm_copy : 1;
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u64 rsvd_189_184 : 6;
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u64 xqe_imm_size : 6;
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u64 later_skip : 6;
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u64 rsvd_171 : 1;
|
||||
u64 first_skip : 7;
|
||||
u64 lpb_sizem1 : 12;
|
||||
u64 spb_ena : 1;
|
||||
u64 rsvd_150_148 : 3;
|
||||
u64 wqe_skip : 2;
|
||||
u64 spb_sizem1 : 6;
|
||||
u64 rsvd_139_128 : 12;
|
||||
#else
|
||||
u64 rsvd_139_128 : 12;
|
||||
u64 spb_sizem1 : 6;
|
||||
u64 wqe_skip : 2;
|
||||
u64 rsvd_150_148 : 3;
|
||||
u64 spb_ena : 1;
|
||||
u64 lpb_sizem1 : 12;
|
||||
u64 first_skip : 7;
|
||||
u64 rsvd_171 : 1;
|
||||
u64 later_skip : 6;
|
||||
u64 xqe_imm_size : 6;
|
||||
u64 rsvd_189_184 : 6;
|
||||
u64 xqe_imm_copy : 1;
|
||||
u64 xqe_hdr_split : 1;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
|
||||
u64 spb_pool_pass : 8;
|
||||
u64 spb_pool_drop : 8;
|
||||
u64 spb_aura_pass : 8;
|
||||
u64 spb_aura_drop : 8;
|
||||
u64 wqe_pool_pass : 8;
|
||||
u64 wqe_pool_drop : 8;
|
||||
u64 xqe_pass : 8;
|
||||
u64 xqe_drop : 8;
|
||||
#else
|
||||
u64 xqe_drop : 8;
|
||||
u64 xqe_pass : 8;
|
||||
u64 wqe_pool_drop : 8;
|
||||
u64 wqe_pool_pass : 8;
|
||||
u64 spb_aura_drop : 8;
|
||||
u64 spb_aura_pass : 8;
|
||||
u64 spb_pool_drop : 8;
|
||||
u64 spb_pool_pass : 8;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W4 */
|
||||
u64 rsvd_319_315 : 5;
|
||||
u64 qint_idx : 7;
|
||||
u64 rq_int_ena : 8;
|
||||
u64 rq_int : 8;
|
||||
u64 rsvd_291_288 : 4;
|
||||
u64 lpb_pool_pass : 8;
|
||||
u64 lpb_pool_drop : 8;
|
||||
u64 lpb_aura_pass : 8;
|
||||
u64 lpb_aura_drop : 8;
|
||||
#else
|
||||
u64 lpb_aura_drop : 8;
|
||||
u64 lpb_aura_pass : 8;
|
||||
u64 lpb_pool_drop : 8;
|
||||
u64 lpb_pool_pass : 8;
|
||||
u64 rsvd_291_288 : 4;
|
||||
u64 rq_int : 8;
|
||||
u64 rq_int_ena : 8;
|
||||
u64 qint_idx : 7;
|
||||
u64 rsvd_319_315 : 5;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W5 */
|
||||
u64 rsvd_383_366 : 18;
|
||||
u64 flow_tagw : 6;
|
||||
u64 bad_utag : 8;
|
||||
u64 good_utag : 8;
|
||||
u64 ltag : 24;
|
||||
#else
|
||||
u64 ltag : 24;
|
||||
u64 good_utag : 8;
|
||||
u64 bad_utag : 8;
|
||||
u64 flow_tagw : 6;
|
||||
u64 rsvd_383_366 : 18;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W6 */
|
||||
u64 rsvd_447_432 : 16;
|
||||
u64 octs : 48;
|
||||
#else
|
||||
u64 octs : 48;
|
||||
u64 rsvd_447_432 : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W7 */
|
||||
u64 rsvd_511_496 : 16;
|
||||
u64 pkts : 48;
|
||||
#else
|
||||
u64 pkts : 48;
|
||||
u64 rsvd_511_496 : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W8 */
|
||||
u64 rsvd_575_560 : 16;
|
||||
u64 drop_octs : 48;
|
||||
#else
|
||||
u64 drop_octs : 48;
|
||||
u64 rsvd_575_560 : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
|
||||
u64 rsvd_639_624 : 16;
|
||||
u64 drop_pkts : 48;
|
||||
#else
|
||||
u64 drop_pkts : 48;
|
||||
u64 rsvd_639_624 : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W10 */
|
||||
u64 rsvd_703_688 : 16;
|
||||
u64 re_pkts : 48;
|
||||
#else
|
||||
u64 re_pkts : 48;
|
||||
u64 rsvd_703_688 : 16;
|
||||
#endif
|
||||
u64 rsvd_767_704; /* W11 */
|
||||
u64 rsvd_831_768; /* W12 */
|
||||
u64 rsvd_895_832; /* W13 */
|
||||
u64 rsvd_959_896; /* W14 */
|
||||
u64 rsvd_1023_960; /* W15 */
|
||||
};
|
||||
|
||||
/* NIX sqe sizes */
|
||||
enum nix_maxsqesz {
|
||||
NIX_MAXSQESZ_W16 = 0x0,
|
||||
NIX_MAXSQESZ_W8 = 0x1,
|
||||
};
|
||||
|
||||
/* NIX SQB caching type */
|
||||
enum nix_stype {
|
||||
NIX_STYPE_STF = 0x0,
|
||||
NIX_STYPE_STT = 0x1,
|
||||
NIX_STYPE_STP = 0x2,
|
||||
};
|
||||
|
||||
/* NIX Send queue context structure */
|
||||
struct nix_sq_ctx_s {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
|
||||
u64 sqe_way_mask : 16;
|
||||
u64 cq : 20;
|
||||
u64 sdp_mcast : 1;
|
||||
u64 substream : 20;
|
||||
u64 qint_idx : 6;
|
||||
u64 ena : 1;
|
||||
#else
|
||||
u64 ena : 1;
|
||||
u64 qint_idx : 6;
|
||||
u64 substream : 20;
|
||||
u64 sdp_mcast : 1;
|
||||
u64 cq : 20;
|
||||
u64 sqe_way_mask : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W1 */
|
||||
u64 sqb_count : 16;
|
||||
u64 default_chan : 12;
|
||||
u64 smq_rr_quantum : 24;
|
||||
u64 sso_ena : 1;
|
||||
u64 xoff : 1;
|
||||
u64 cq_ena : 1;
|
||||
u64 smq : 9;
|
||||
#else
|
||||
u64 smq : 9;
|
||||
u64 cq_ena : 1;
|
||||
u64 xoff : 1;
|
||||
u64 sso_ena : 1;
|
||||
u64 smq_rr_quantum : 24;
|
||||
u64 default_chan : 12;
|
||||
u64 sqb_count : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W2 */
|
||||
u64 rsvd_191 : 1;
|
||||
u64 sqe_stype : 2;
|
||||
u64 sq_int_ena : 8;
|
||||
u64 sq_int : 8;
|
||||
u64 sqb_aura : 20;
|
||||
u64 smq_rr_count : 25;
|
||||
#else
|
||||
u64 smq_rr_count : 25;
|
||||
u64 sqb_aura : 20;
|
||||
u64 sq_int : 8;
|
||||
u64 sq_int_ena : 8;
|
||||
u64 sqe_stype : 2;
|
||||
u64 rsvd_191 : 1;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W3 */
|
||||
u64 rsvd_255_253 : 3;
|
||||
u64 smq_next_sq_vld : 1;
|
||||
u64 smq_pend : 1;
|
||||
u64 smenq_next_sqb_vld : 1;
|
||||
u64 head_offset : 6;
|
||||
u64 smenq_offset : 6;
|
||||
u64 tail_offset : 6;
|
||||
u64 smq_lso_segnum : 8;
|
||||
u64 smq_next_sq : 20;
|
||||
u64 mnq_dis : 1;
|
||||
u64 lmt_dis : 1;
|
||||
u64 cq_limit : 8;
|
||||
u64 max_sqe_size : 2;
|
||||
#else
|
||||
u64 max_sqe_size : 2;
|
||||
u64 cq_limit : 8;
|
||||
u64 lmt_dis : 1;
|
||||
u64 mnq_dis : 1;
|
||||
u64 smq_next_sq : 20;
|
||||
u64 smq_lso_segnum : 8;
|
||||
u64 tail_offset : 6;
|
||||
u64 smenq_offset : 6;
|
||||
u64 head_offset : 6;
|
||||
u64 smenq_next_sqb_vld : 1;
|
||||
u64 smq_pend : 1;
|
||||
u64 smq_next_sq_vld : 1;
|
||||
u64 rsvd_255_253 : 3;
|
||||
#endif
|
||||
u64 next_sqb : 64;/* W4 */
|
||||
u64 tail_sqb : 64;/* W5 */
|
||||
u64 smenq_sqb : 64;/* W6 */
|
||||
u64 smenq_next_sqb : 64;/* W7 */
|
||||
u64 head_sqb : 64;/* W8 */
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W9 */
|
||||
u64 rsvd_639_630 : 10;
|
||||
u64 vfi_lso_vld : 1;
|
||||
u64 vfi_lso_vlan1_ins_ena : 1;
|
||||
u64 vfi_lso_vlan0_ins_ena : 1;
|
||||
u64 vfi_lso_mps : 14;
|
||||
u64 vfi_lso_sb : 8;
|
||||
u64 vfi_lso_sizem1 : 3;
|
||||
u64 vfi_lso_total : 18;
|
||||
u64 rsvd_583_576 : 8;
|
||||
#else
|
||||
u64 rsvd_583_576 : 8;
|
||||
u64 vfi_lso_total : 18;
|
||||
u64 vfi_lso_sizem1 : 3;
|
||||
u64 vfi_lso_sb : 8;
|
||||
u64 vfi_lso_mps : 14;
|
||||
u64 vfi_lso_vlan0_ins_ena : 1;
|
||||
u64 vfi_lso_vlan1_ins_ena : 1;
|
||||
u64 vfi_lso_vld : 1;
|
||||
u64 rsvd_639_630 : 10;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W10 */
|
||||
u64 rsvd_703_658 : 46;
|
||||
u64 scm_lso_rem : 18;
|
||||
#else
|
||||
u64 scm_lso_rem : 18;
|
||||
u64 rsvd_703_658 : 46;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W11 */
|
||||
u64 rsvd_767_752 : 16;
|
||||
u64 octs : 48;
|
||||
#else
|
||||
u64 octs : 48;
|
||||
u64 rsvd_767_752 : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W12 */
|
||||
u64 rsvd_831_816 : 16;
|
||||
u64 pkts : 48;
|
||||
#else
|
||||
u64 pkts : 48;
|
||||
u64 rsvd_831_816 : 16;
|
||||
#endif
|
||||
u64 rsvd_895_832 : 64;/* W13 */
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W14 */
|
||||
u64 rsvd_959_944 : 16;
|
||||
u64 dropped_octs : 48;
|
||||
#else
|
||||
u64 dropped_octs : 48;
|
||||
u64 rsvd_959_944 : 16;
|
||||
#endif
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W15 */
|
||||
u64 rsvd_1023_1008 : 16;
|
||||
u64 dropped_pkts : 48;
|
||||
#else
|
||||
u64 dropped_pkts : 48;
|
||||
u64 rsvd_1023_1008 : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* NIX Receive side scaling entry structure*/
|
||||
struct nix_rsse_s {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
uint32_t reserved_20_31 : 12;
|
||||
uint32_t rq : 20;
|
||||
#else
|
||||
uint32_t rq : 20;
|
||||
uint32_t reserved_20_31 : 12;
|
||||
|
||||
#endif
|
||||
};
|
||||
|
||||
/* NIX receive multicast/mirror entry structure */
|
||||
struct nix_rx_mce_s {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD) /* W0 */
|
||||
uint64_t next : 16;
|
||||
uint64_t pf_func : 16;
|
||||
uint64_t rsvd_31_24 : 8;
|
||||
uint64_t index : 20;
|
||||
uint64_t eol : 1;
|
||||
uint64_t rsvd_2 : 1;
|
||||
uint64_t op : 2;
|
||||
#else
|
||||
uint64_t op : 2;
|
||||
uint64_t rsvd_2 : 1;
|
||||
uint64_t eol : 1;
|
||||
uint64_t index : 20;
|
||||
uint64_t rsvd_31_24 : 8;
|
||||
uint64_t pf_func : 16;
|
||||
uint64_t next : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
enum nix_lsoalg {
|
||||
NIX_LSOALG_NOP,
|
||||
NIX_LSOALG_ADD_SEGNUM,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user