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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/display: Reuse dcn2 registers
[Why & How] Use dcn2 blender, shaper, 3dlut registers Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Vitaly Prosyak
Alex Deucher
parent
649828f718
commit
ff344c8d2a
@ -30,16 +30,20 @@
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#define TO_DCN20_DPP(dpp)\
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container_of(dpp, struct dcn20_dpp, base)
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#define TF_REG_LIST_DCN20(id) \
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TF_REG_LIST_DCN(id), \
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#define TF_REG_LIST_DCN20_COMMON_UPDATED(id) \
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SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
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SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
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SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
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SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
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SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
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SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
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SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)
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#define TF_REG_LIST_DCN20_COMMON(id) \
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SRI(CM_BLNDGAM_CONTROL, CM, id), \
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SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
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SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \
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SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \
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SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
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SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
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SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
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SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \
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SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \
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SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \
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@ -66,9 +70,6 @@
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SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \
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SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \
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SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \
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SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
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SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
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SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id), \
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SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \
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SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \
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SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \
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@ -147,7 +148,12 @@
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SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \
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SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \
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SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \
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SRI(CM_SHAPER_LUT_INDEX, CM, id), \
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SRI(CM_SHAPER_LUT_INDEX, CM, id)
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#define TF_REG_LIST_DCN20(id) \
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TF_REG_LIST_DCN(id), \
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TF_REG_LIST_DCN20_COMMON(id), \
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TF_REG_LIST_DCN20_COMMON_UPDATED(id), \
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SRI(CURSOR_CONTROL, CURSOR0_, id), \
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SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
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SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
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@ -166,27 +172,41 @@
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SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
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SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
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#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
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TF_REG_LIST_SH_MASK_DCN(mask_sh), \
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#define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\
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TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \
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TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
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#define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\
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TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
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@ -261,18 +281,9 @@
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TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
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@ -341,9 +352,6 @@
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TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \
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TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \
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TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \
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@ -356,7 +364,6 @@
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TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \
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TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \
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TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \
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TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \
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TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \
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TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \
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TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \
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@ -521,9 +528,14 @@
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TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
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TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \
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TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \
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TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, mask_sh), \
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TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \
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TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh), \
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TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh)
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#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
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TF_REG_LIST_SH_MASK_DCN(mask_sh), \
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TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
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TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
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TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \
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TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
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TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
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@ -560,6 +572,7 @@
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TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
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TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
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#define TF_REG_FIELD_LIST_DCN2_0(type) \
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TF_REG_FIELD_LIST(type) \
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type CM_BLNDGAM_LUT_DATA; \
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@ -593,6 +606,7 @@
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type OBUF_MEM_PWR_FORCE;\
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type LUT_MEM_PWR_FORCE
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struct dcn2_dpp_shift {
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TF_REG_FIELD_LIST_DCN2_0(uint8_t);
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};
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@ -508,7 +508,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
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}
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static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
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void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
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{
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DC_LOGGER_INIT(dc->ctx->logger);
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@ -688,7 +688,7 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
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return true;
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}
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static bool dcn20_set_blend_lut(
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bool dcn20_set_blend_lut(
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struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
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{
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struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
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@ -710,7 +710,7 @@ static bool dcn20_set_blend_lut(
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return result;
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}
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static bool dcn20_set_shaper_3dlut(
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bool dcn20_set_shaper_3dlut(
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struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
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{
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struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
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@ -923,7 +923,7 @@ static void dcn20_power_on_plane(
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}
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}
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static void dcn20_enable_plane(
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void dcn20_enable_plane(
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struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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struct dc_state *context)
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@ -1021,7 +1021,7 @@ void dcn20_pipe_control_lock_global(
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}
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}
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static void dcn20_pipe_control_lock(
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void dcn20_pipe_control_lock(
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struct dc *dc,
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struct pipe_ctx *pipe,
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bool lock)
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@ -96,4 +96,18 @@ void dcn20_init_blank(
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struct dc *dc,
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struct timing_generator *tg);
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void dcn20_display_init(struct dc *dc);
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void dcn20_pipe_control_lock(
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struct dc *dc,
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struct pipe_ctx *pipe,
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bool lock);
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void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
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||||
void dcn20_enable_plane(
|
||||
struct dc *dc,
|
||||
struct pipe_ctx *pipe_ctx,
|
||||
struct dc_state *context);
|
||||
bool dcn20_set_blend_lut(
|
||||
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
|
||||
bool dcn20_set_shaper_3dlut(
|
||||
struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
|
||||
|
||||
#endif /* __DC_HWSS_DCN20_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user