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drm/amdgpu: use different irq ring ID for Vega20 page queues

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Vega20 uses ring id 1 for page queues EOP irq while previous
ASICs take ring id 3.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2018-12-10 15:12:29 +08:00 committed by Alex Deucher
parent c713a46145
commit fefdc6cc0a
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
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@ -1706,13 +1706,15 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
amdgpu_fence_process(&adev->sdma.instance[instance].ring);
break;
case 1:
/* XXX compute */
if (adev->asic_type == CHIP_VEGA20)
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
case 2:
/* XXX compute */
break;
case 3:
amdgpu_fence_process(&adev->sdma.instance[instance].page);
if (adev->asic_type != CHIP_VEGA20)
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
}
return 0;