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mlxsw: spectrum_buffers: Add Spectrum-2 shared buffer configuration
Customize the tables related to shared buffer configuration to match the current recommendation for Spectrum-2 systems. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Petr Machata
David S. Miller
parent
13f35cc424
commit
fe099bf682
@ -49,7 +49,7 @@ struct mlxsw_sp_sb_pool_des {
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};
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/* Order ingress pools before egress pools. */
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static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_pool_dess[] = {
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static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = {
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{MLXSW_REG_SBXX_DIR_INGRESS, 0},
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{MLXSW_REG_SBXX_DIR_INGRESS, 1},
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{MLXSW_REG_SBXX_DIR_INGRESS, 2},
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@ -61,6 +61,17 @@ static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_pool_dess[] = {
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{MLXSW_REG_SBXX_DIR_EGRESS, 15},
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};
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static const struct mlxsw_sp_sb_pool_des mlxsw_sp2_sb_pool_dess[] = {
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{MLXSW_REG_SBXX_DIR_INGRESS, 0},
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{MLXSW_REG_SBXX_DIR_INGRESS, 1},
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{MLXSW_REG_SBXX_DIR_INGRESS, 2},
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{MLXSW_REG_SBXX_DIR_INGRESS, 3},
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{MLXSW_REG_SBXX_DIR_EGRESS, 0},
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{MLXSW_REG_SBXX_DIR_EGRESS, 1},
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{MLXSW_REG_SBXX_DIR_EGRESS, 2},
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{MLXSW_REG_SBXX_DIR_EGRESS, 3},
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};
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#define MLXSW_SP_SB_ING_TC_COUNT 8
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#define MLXSW_SP_SB_EG_TC_COUNT 16
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@ -366,32 +377,53 @@ static void mlxsw_sp_sb_ports_fini(struct mlxsw_sp *mlxsw_sp)
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kfree(mlxsw_sp->sb->ports);
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}
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#define MLXSW_SP_SB_PR_INGRESS_SIZE 12440000
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#define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
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#define MLXSW_SP_SB_PR_EGRESS_SIZE 13232000
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#define MLXSW_SP_SB_PR(_mode, _size) \
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{ \
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.mode = _mode, \
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.size = _size, \
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}
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static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs[] = {
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#define MLXSW_SP1_SB_PR_INGRESS_SIZE 12440000
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#define MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
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#define MLXSW_SP1_SB_PR_EGRESS_SIZE 13232000
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static const struct mlxsw_sp_sb_pr mlxsw_sp1_sb_prs[] = {
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/* Ingress pools. */
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
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MLXSW_SP_SB_PR_INGRESS_SIZE),
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MLXSW_SP1_SB_PR_INGRESS_SIZE),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
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MLXSW_SP_SB_PR_INGRESS_MNG_SIZE),
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MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE),
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/* Egress pools. */
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, MLXSW_SP_SB_PR_EGRESS_SIZE),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
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MLXSW_SP1_SB_PR_EGRESS_SIZE),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI),
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};
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#define MLXSW_SP2_SB_PR_INGRESS_SIZE 40960000
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#define MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
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#define MLXSW_SP2_SB_PR_EGRESS_SIZE 40960000
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static const struct mlxsw_sp_sb_pr mlxsw_sp2_sb_prs[] = {
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/* Ingress pools. */
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
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MLXSW_SP2_SB_PR_INGRESS_SIZE),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
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MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE),
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/* Egress pools. */
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
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MLXSW_SP2_SB_PR_EGRESS_SIZE),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
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MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
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};
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static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
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const struct mlxsw_sp_sb_pr *prs,
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size_t prs_len)
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@ -424,7 +456,7 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
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.pool_index = _pool, \
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}
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static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
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static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] = {
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MLXSW_SP_SB_CM(10000, 8, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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@ -437,7 +469,20 @@ static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
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MLXSW_SP_SB_CM(20000, 1, 3),
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};
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static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
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static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] = {
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MLXSW_SP_SB_CM(0, 7, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
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MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
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MLXSW_SP_SB_CM(20000, 1, 3),
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};
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static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] = {
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MLXSW_SP_SB_CM(1500, 9, 4),
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MLXSW_SP_SB_CM(1500, 9, 4),
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MLXSW_SP_SB_CM(1500, 9, 4),
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@ -457,6 +502,26 @@ static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
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MLXSW_SP_SB_CM(1, 0xff, 4),
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};
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static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] = {
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(0, 7, 4),
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MLXSW_SP_SB_CM(1, 0xff, 4),
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};
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#define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 4)
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static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
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@ -575,7 +640,7 @@ static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
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.max_buff = _max_buff, \
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}
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static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
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static const struct mlxsw_sp_sb_pm mlxsw_sp1_sb_pms[] = {
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/* Ingress pools. */
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MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
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MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
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@ -589,6 +654,19 @@ static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
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MLXSW_SP_SB_PM(10000, 90000),
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};
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static const struct mlxsw_sp_sb_pm mlxsw_sp2_sb_pms[] = {
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/* Ingress pools. */
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MLXSW_SP_SB_PM(0, 7),
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MLXSW_SP_SB_PM(0, 0),
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MLXSW_SP_SB_PM(0, 0),
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MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
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/* Egress pools. */
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MLXSW_SP_SB_PM(0, 7),
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MLXSW_SP_SB_PM(0, 0),
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MLXSW_SP_SB_PM(0, 0),
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MLXSW_SP_SB_PM(0, 0),
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};
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static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
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{
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struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
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@ -680,32 +758,32 @@ static void mlxsw_sp_pool_count(struct mlxsw_sp *mlxsw_sp,
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}
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const struct mlxsw_sp_sb_vals mlxsw_sp1_sb_vals = {
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.pool_count = ARRAY_SIZE(mlxsw_sp_sb_pool_dess),
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.pool_dess = mlxsw_sp_sb_pool_dess,
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.pms = mlxsw_sp_sb_pms,
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.prs = mlxsw_sp_sb_prs,
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.pool_count = ARRAY_SIZE(mlxsw_sp1_sb_pool_dess),
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.pool_dess = mlxsw_sp1_sb_pool_dess,
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.pms = mlxsw_sp1_sb_pms,
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.prs = mlxsw_sp1_sb_prs,
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.mms = mlxsw_sp_sb_mms,
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.cms_ingress = mlxsw_sp_sb_cms_ingress,
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.cms_egress = mlxsw_sp_sb_cms_egress,
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.cms_ingress = mlxsw_sp1_sb_cms_ingress,
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.cms_egress = mlxsw_sp1_sb_cms_egress,
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.cms_cpu = mlxsw_sp_cpu_port_sb_cms,
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.mms_count = ARRAY_SIZE(mlxsw_sp_sb_mms),
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.cms_ingress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_ingress),
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.cms_egress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_egress),
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.cms_ingress_count = ARRAY_SIZE(mlxsw_sp1_sb_cms_ingress),
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.cms_egress_count = ARRAY_SIZE(mlxsw_sp1_sb_cms_egress),
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.cms_cpu_count = ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms),
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};
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const struct mlxsw_sp_sb_vals mlxsw_sp2_sb_vals = {
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.pool_count = ARRAY_SIZE(mlxsw_sp_sb_pool_dess),
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.pool_dess = mlxsw_sp_sb_pool_dess,
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.pms = mlxsw_sp_sb_pms,
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.prs = mlxsw_sp_sb_prs,
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.pool_count = ARRAY_SIZE(mlxsw_sp2_sb_pool_dess),
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.pool_dess = mlxsw_sp2_sb_pool_dess,
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.pms = mlxsw_sp2_sb_pms,
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.prs = mlxsw_sp2_sb_prs,
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.mms = mlxsw_sp_sb_mms,
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.cms_ingress = mlxsw_sp_sb_cms_ingress,
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.cms_egress = mlxsw_sp_sb_cms_egress,
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.cms_ingress = mlxsw_sp2_sb_cms_ingress,
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.cms_egress = mlxsw_sp2_sb_cms_egress,
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.cms_cpu = mlxsw_sp_cpu_port_sb_cms,
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.mms_count = ARRAY_SIZE(mlxsw_sp_sb_mms),
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.cms_ingress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_ingress),
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.cms_egress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_egress),
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.cms_ingress_count = ARRAY_SIZE(mlxsw_sp2_sb_cms_ingress),
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.cms_egress_count = ARRAY_SIZE(mlxsw_sp2_sb_cms_egress),
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.cms_cpu_count = ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms),
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};
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