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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 02:46:46 +07:00
drm/amdgpu: cleanup vm_size handling
It's pointless to have the same value twice, just always use max_pfn. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drivers/gpu/drm/amd/amdgpu
@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
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* @adev: amdgpu_device pointer
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* @vm_size: the default vm size if it's set auto
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*/
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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uint32_t fragment_size_default)
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{
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/* adjust vm size firstly */
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if (amdgpu_vm_size == -1)
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adev->vm_manager.vm_size = vm_size;
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else
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adev->vm_manager.vm_size = amdgpu_vm_size;
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if (amdgpu_vm_size != -1)
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vm_size = amdgpu_vm_size;
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adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
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/* block size depends on vm size */
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if (amdgpu_vm_block_size == -1)
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adev->vm_manager.block_size =
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amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
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amdgpu_vm_get_block_size(vm_size);
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else
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adev->vm_manager.block_size = amdgpu_vm_block_size;
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amdgpu_vm_set_fragment_size(adev, fragment_size_default);
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DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
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adev->vm_manager.vm_size, adev->vm_manager.block_size,
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adev->vm_manager.fragment_size);
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DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
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vm_size, adev->vm_manager.block_size,
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adev->vm_manager.fragment_size);
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}
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/**
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@ -221,7 +221,6 @@ struct amdgpu_vm_manager {
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uint64_t max_pfn;
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uint32_t num_level;
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uint64_t vm_size;
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uint32_t block_size;
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uint32_t fragment_size;
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/* vram base address for page table entry */
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@ -313,9 +312,9 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
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void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va);
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void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
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uint32_t fragment_size_default);
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
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uint32_t fragment_size_default);
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uint32_t fragment_size_default);
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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uint32_t fragment_size_default);
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int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
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bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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struct amdgpu_job *job);
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@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle)
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return r;
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amdgpu_vm_adjust_size(adev, 64, 9);
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adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
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adev->mc.mc_mask = 0xffffffffffULL;
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@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle)
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* Max GPUVM size for cayman and SI is 40 bits.
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*/
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amdgpu_vm_adjust_size(adev, 64, 9);
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adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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@ -1075,7 +1075,6 @@ static int gmc_v8_0_sw_init(void *handle)
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* Max GPUVM size for cayman and SI is 40 bits.
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*/
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amdgpu_vm_adjust_size(adev, 64, 9);
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adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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@ -564,7 +564,7 @@ static int gmc_v9_0_sw_init(void *handle)
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case CHIP_RAVEN:
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adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
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adev->vm_manager.vm_size = 1U << 18;
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adev->vm_manager.max_pfn = 1ULL << 36;
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adev->vm_manager.block_size = 9;
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adev->vm_manager.num_level = 3;
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amdgpu_vm_set_fragment_size(adev, 9);
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@ -582,7 +582,7 @@ static int gmc_v9_0_sw_init(void *handle)
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* vm size is 256TB (48bit), maximum size of Vega10,
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* block size 512 (9bit)
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*/
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adev->vm_manager.vm_size = 1U << 18;
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adev->vm_manager.max_pfn = 1ULL << 36;
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adev->vm_manager.block_size = 9;
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adev->vm_manager.num_level = 3;
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amdgpu_vm_set_fragment_size(adev, 9);
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@ -591,10 +591,9 @@ static int gmc_v9_0_sw_init(void *handle)
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break;
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}
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DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
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adev->vm_manager.vm_size,
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adev->vm_manager.block_size,
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adev->vm_manager.fragment_size);
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DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
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adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
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adev->vm_manager.fragment_size);
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/* This interrupt is VMC page fault.*/
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r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
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@ -605,8 +604,6 @@ static int gmc_v9_0_sw_init(void *handle)
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if (r)
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return r;
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adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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* internal address space.
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