mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 11:20:49 +07:00
sparc64: Increase max_phys_bits to 51 and VA bits to 53 for M8.
On M8 chips, use a max_phys_bits value of 51. Also, M8 supports VA bits up to 54 bits. However, for now restrict VA bits to 53 due to 4-level pagetable limitation. Signed-off-by: Vijay Kumar <vijay.ac.kumar@oracle.com> Reviewed-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
7d484acb2f
commit
fdaccf74fe
@ -1944,12 +1944,22 @@ static void __init setup_page_offset(void)
|
||||
break;
|
||||
case SUN4V_CHIP_SPARC_M7:
|
||||
case SUN4V_CHIP_SPARC_SN:
|
||||
default:
|
||||
/* M7 and later support 52-bit virtual addresses. */
|
||||
sparc64_va_hole_top = 0xfff8000000000000UL;
|
||||
sparc64_va_hole_bottom = 0x0008000000000000UL;
|
||||
max_phys_bits = 49;
|
||||
break;
|
||||
case SUN4V_CHIP_SPARC_M8:
|
||||
default:
|
||||
/* M8 and later support 54-bit virtual addresses.
|
||||
* However, restricting M8 and above VA bits to 53
|
||||
* as 4-level page table cannot support more than
|
||||
* 53 VA bits.
|
||||
*/
|
||||
sparc64_va_hole_top = 0xfff0000000000000UL;
|
||||
sparc64_va_hole_bottom = 0x0010000000000000UL;
|
||||
max_phys_bits = 51;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user