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drm/nouveau/msppp: rename from ppp (no binary change)

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Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-01-14 12:26:28 +10:00
parent d5752b9b86
commit fd8666f7db
25 changed files with 108 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@ -128,7 +128,7 @@ struct nv_device_v0 {
#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL
#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
@ -349,7 +349,7 @@ struct kepler_channel_gpfifo_a_v0 {
__u8 version;
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -51,7 +51,7 @@ enum nv_subdev_type {
NVDEV_ENGINE_VP,
NVDEV_ENGINE_CIPHER,
NVDEV_ENGINE_BSP,
NVDEV_ENGINE_PPP,
NVDEV_ENGINE_MSPPP,
NVDEV_ENGINE_CE0,
NVDEV_ENGINE_CE1,
NVDEV_ENGINE_CE2,

7
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __NOUVEAU_MSPPP_H__
#define __NOUVEAU_MSPPP_H__
extern struct nouveau_oclass nv98_msppp_oclass;
extern struct nouveau_oclass nvc0_msppp_oclass;
#endif

7
drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
View File

@ -1,7 +0,0 @@
#ifndef __NOUVEAU_PPP_H__
#define __NOUVEAU_PPP_H__
extern struct nouveau_oclass nv98_ppp_oclass;
extern struct nouveau_oclass nvc0_ppp_oclass;
#endif

2
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
View File

@ -12,7 +12,7 @@ include $(src)/nvkm/engine/gr/Kbuild
include $(src)/nvkm/engine/mpeg/Kbuild
include $(src)/nvkm/engine/msvld/Kbuild
include $(src)/nvkm/engine/pm/Kbuild
include $(src)/nvkm/engine/ppp/Kbuild
include $(src)/nvkm/engine/msppp/Kbuild
include $(src)/nvkm/engine/sec/Kbuild
include $(src)/nvkm/engine/software/Kbuild
include $(src)/nvkm/engine/vp/Kbuild

2
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -234,7 +234,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP,
[NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER,
[NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP,
[NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP,
[NVDEV_ENGINE_MSPPP] = NV_DEVICE_V0_DISABLE_MSPPP,
[NVDEV_ENGINE_CE0] = NV_DEVICE_V0_DISABLE_CE0,
[NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1,
[NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2,

6
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -52,7 +52,7 @@
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/msppp.h>
#include <engine/pm.h>
int
@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device)
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
case 0x124:
@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
#endif
break;
default:

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -51,7 +51,7 @@
#include <engine/sec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/ppp.h>
#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/pm.h>
@ -256,7 +256,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@ -343,7 +343,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
break;
@ -373,7 +373,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@ -403,7 +403,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@ -433,7 +433,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;
@ -463,7 +463,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nva3_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass;

20
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View File

@ -50,7 +50,7 @@
#include <engine/vp.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/ppp.h>
#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/pm.h>
@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View File

@ -52,7 +52,7 @@
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/msppp.h>
#include <engine/pm.h>
int
@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe7:
@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xe6:
@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
break;
case 0xea:
@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0xf1:
@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
break;
case 0x106:
@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
case 0x108:
device->cname = "GK208";
@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
break;
default:
nv_fatal(device, "unknown Kepler chipset\n");

10
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
View File

@ -58,7 +58,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : addr = 0x0020; break;
case NVDEV_ENGINE_VP : addr = 0x0040; break;
case NVDEV_ENGINE_PPP :
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
@ -96,7 +96,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_SW : return 0;
case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
case NVDEV_ENGINE_PPP :
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
@ -145,7 +145,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_SW : context |= 0x00000000; break;
case NVDEV_ENGINE_GR : context |= 0x00100000; break;
case NVDEV_ENGINE_MPEG :
case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
case NVDEV_ENGINE_ME :
case NVDEV_ENGINE_CE0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
@ -195,7 +195,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
@ -270,7 +270,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_SEC) |
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_MSPPP) |
(1ULL << NVDEV_ENGINE_CE0) |
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
View File

@ -126,7 +126,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@ -163,7 +163,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@ -216,7 +216,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_CE1) |
(1ULL << NVDEV_ENGINE_MSVLD) |
(1ULL << NVDEV_ENGINE_VP) |
(1ULL << NVDEV_ENGINE_PPP), &chan);
(1ULL << NVDEV_ENGINE_MSPPP), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@ -383,7 +383,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
switch (engn) {
case NVDEV_ENGINE_GR : engn = 0; break;
case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_MSPPP: engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
@ -400,7 +400,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
switch (engn) {
case 0: engn = NVDEV_ENGINE_GR; break;
case 1: engn = NVDEV_ENGINE_MSVLD; break;
case 2: engn = NVDEV_ENGINE_PPP; break;
case 2: engn = NVDEV_ENGINE_MSPPP; break;
case 3: engn = NVDEV_ENGINE_VP; break;
case 4: engn = NVDEV_ENGINE_CE0; break;
case 5: engn = NVDEV_ENGINE_CE1; break;
@ -549,7 +549,7 @@ nvc0_fifo_fault_engine[] = {
{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PCOUNTER" },
{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
{ 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
@ -582,7 +582,7 @@ nvc0_fifo_fault_hubclient[] = {
{ 0x07, "BAR_READ" },
{ 0x08, "BAR_WRITE" },
{ 0x0b, "PVP" },
{ 0x0c, "PPPP" },
{ 0x0c, "PMSPPP" },
{ 0x0d, "PMSVLD" },
{ 0x11, "PCOUNTER" },
{ 0x12, "PDAEMON" },
@ -940,7 +940,7 @@ nvc0_fifo_init(struct nouveau_object *object)
if (priv->spoon_nr >= 3) {
nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
nv_wr32(priv, 0x002210, ~(1 << 1)); /* PMSPP */
nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */
nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */

10
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
View File

@ -49,7 +49,7 @@ static const struct {
_(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_CE2)),
_(NVDEV_ENGINE_VP , 0),
_(NVDEV_ENGINE_PPP , 0),
_(NVDEV_ENGINE_MSPPP , 0),
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
_(NVDEV_ENGINE_CE1 , 0),
@ -151,7 +151,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@ -189,7 +189,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
case NVDEV_ENGINE_GR : addr = 0x0210; break;
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
case NVDEV_ENGINE_VP : addr = 0x0250; break;
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
default:
return -EINVAL;
}
@ -417,7 +417,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
case NVDEV_ENGINE_GR :
case NVDEV_ENGINE_CE2 : engn = 0; break;
case NVDEV_ENGINE_MSVLD: engn = 1; break;
case NVDEV_ENGINE_PPP : engn = 2; break;
case NVDEV_ENGINE_MSPPP: engn = 2; break;
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
@ -620,7 +620,7 @@ nve0_fifo_fault_engine[] = {
{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x13, "PERF" },
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },

2
drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild Normal file
View File

@ -0,0 +1,2 @@
nvkm-y += nvkm/engine/msppp/nv98.o
nvkm-y += nvkm/engine/msppp/nvc0.o

38
drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c → drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
View File

@ -23,30 +23,30 @@
*/
#include <engine/falcon.h>
#include <engine/ppp.h>
#include <engine/msppp.h>
struct nv98_ppp_priv {
struct nv98_msppp_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
* PPP object classes
* MSPPP object classes
******************************************************************************/
static struct nouveau_oclass
nv98_ppp_sclass[] = {
nv98_msppp_sclass[] = {
{ 0x88b3, &nouveau_object_ofuncs },
{ 0x85b3, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
* PPPP context
* PMSPPP context
******************************************************************************/
static struct nouveau_oclass
nv98_ppp_cclass = {
.handle = NV_ENGCTX(PPP, 0x98),
nv98_msppp_cclass = {
.handle = NV_ENGCTX(MSPPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@ -58,13 +58,13 @@ nv98_ppp_cclass = {
};
/*******************************************************************************
* PPPP engine/subdev functions
* PMSPPP engine/subdev functions
******************************************************************************/
static int
nv98_ppp_init(struct nouveau_object *object)
nv98_msppp_init(struct nouveau_object *object)
{
struct nv98_ppp_priv *priv = (void *)object;
struct nv98_msppp_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@ -77,32 +77,32 @@ nv98_ppp_init(struct nouveau_object *object)
}
static int
nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv98_ppp_priv *priv;
struct nv98_msppp_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
"PPPP", "ppp", &priv);
"PMSPPP", "msppp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00400002;
nv_engine(priv)->cclass = &nv98_ppp_cclass;
nv_engine(priv)->sclass = nv98_ppp_sclass;
nv_engine(priv)->cclass = &nv98_msppp_cclass;
nv_engine(priv)->sclass = nv98_msppp_sclass;
return 0;
}
struct nouveau_oclass
nv98_ppp_oclass = {
.handle = NV_ENGINE(PPP, 0x98),
nv98_msppp_oclass = {
.handle = NV_ENGINE(MSPPP, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv98_ppp_ctor,
.ctor = nv98_msppp_ctor,
.dtor = _nouveau_falcon_dtor,
.init = nv98_ppp_init,
.init = nv98_msppp_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,

38
drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
View File

@ -23,29 +23,29 @@
*/
#include <engine/falcon.h>
#include <engine/ppp.h>
#include <engine/msppp.h>
struct nvc0_ppp_priv {
struct nvc0_msppp_priv {
struct nouveau_falcon base;
};
/*******************************************************************************
* PPP object classes
* MSPPP object classes
******************************************************************************/
static struct nouveau_oclass
nvc0_ppp_sclass[] = {
nvc0_msppp_sclass[] = {
{ 0x90b3, &nouveau_object_ofuncs },
{},
};
/*******************************************************************************
* PPPP context
* PMSPPP context
******************************************************************************/
static struct nouveau_oclass
nvc0_ppp_cclass = {
.handle = NV_ENGCTX(PPP, 0xc0),
nvc0_msppp_cclass = {
.handle = NV_ENGCTX(MSPPP, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
@ -57,13 +57,13 @@ nvc0_ppp_cclass = {
};
/*******************************************************************************
* PPPP engine/subdev functions
* PMSPPP engine/subdev functions
******************************************************************************/
static int
nvc0_ppp_init(struct nouveau_object *object)
nvc0_msppp_init(struct nouveau_object *object)
{
struct nvc0_ppp_priv *priv = (void *)object;
struct nvc0_msppp_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
@ -76,33 +76,33 @@ nvc0_ppp_init(struct nouveau_object *object)
}
static int
nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_ppp_priv *priv;
struct nvc0_msppp_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
"PPPP", "ppp", &priv);
"PMSPPP", "msppp", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nouveau_falcon_intr;
nv_engine(priv)->cclass = &nvc0_ppp_cclass;
nv_engine(priv)->sclass = nvc0_ppp_sclass;
nv_engine(priv)->cclass = &nvc0_msppp_cclass;
nv_engine(priv)->sclass = nvc0_msppp_sclass;
return 0;
}
struct nouveau_oclass
nvc0_ppp_oclass = {
.handle = NV_ENGINE(PPP, 0xc0),
nvc0_msppp_oclass = {
.handle = NV_ENGINE(MSPPP, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_ppp_ctor,
.ctor = nvc0_msppp_ctor,
.dtor = _nouveau_falcon_dtor,
.init = nvc0_ppp_init,
.init = nvc0_msppp_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,

2
drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
View File

@ -1,2 +0,0 @@
nvkm-y += nvkm/engine/ppp/nv98.o
nvkm-y += nvkm/engine/ppp/nvc0.o

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
View File

@ -35,7 +35,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
disable |= (1ULL << NVDEV_ENGINE_PPP);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
View File

@ -68,7 +68,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
View File

@ -34,7 +34,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
View File

@ -71,7 +71,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
if (r022500 & 0x00000002) {
disable |= (1ULL << NVDEV_ENGINE_VP);
disable |= (1ULL << NVDEV_ENGINE_PPP);
disable |= (1ULL << NVDEV_ENGINE_MSPPP);
}
if (r022500 & 0x00000004)

4
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
View File

@ -101,7 +101,7 @@ static const struct nouveau_enum vm_client[] = {
{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
{ 0x00000004, "PFIFO_WRITE", NULL },
{ 0x00000005, "CCACHE", vm_ccache_subclients },
{ 0x00000006, "PPPP", NULL },
{ 0x00000006, "PMSPPP", NULL },
{ 0x00000007, "CLIPID", NULL },
{ 0x00000008, "PFIFO_READ", NULL },
{ 0x00000009, "VFETCH", NULL },
@ -121,7 +121,7 @@ static const struct nouveau_enum vm_engine[] = {
{ 0x00000004, "PEEPHOLE", NULL },
{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
{ 0x00000006, "BAR", vm_bar_subclients },
{ 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
View File

@ -27,7 +27,7 @@
static const struct nouveau_mc_intr
nv98_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
{ 0x00000001, NVDEV_ENGINE_PPP },
{ 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000100, NVDEV_ENGINE_FIFO },
{ 0x00001000, NVDEV_ENGINE_GR },
{ 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */

2
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
View File

@ -27,7 +27,7 @@
const struct nouveau_mc_intr
nvc0_mc_intr[] = {
{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
{ 0x00000001, NVDEV_ENGINE_PPP },
{ 0x00000001, NVDEV_ENGINE_MSPPP },
{ 0x00000020, NVDEV_ENGINE_CE0 },
{ 0x00000040, NVDEV_ENGINE_CE1 },
{ 0x00000080, NVDEV_ENGINE_CE2 },

2
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
View File

@ -174,7 +174,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
case NVDEV_ENGINE_GR : vme = 0x00; break;
case NVDEV_ENGINE_VP : vme = 0x01; break;
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
case NVDEV_ENGINE_PPP :
case NVDEV_ENGINE_MSPPP :
case NVDEV_ENGINE_MPEG : vme = 0x08; break;
case NVDEV_ENGINE_BSP :
case NVDEV_ENGINE_MSVLD : vme = 0x09; break;