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drm/amdgpu: enable 4 level page table on raven (v3)
v1: enable 4 level-page table on raven v2: add back legacy 2 level page table on raven v3: set num_level in initial switch statement Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -537,10 +537,20 @@ static int gmc_v9_0_sw_init(void *handle)
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spin_lock_init(&adev->mc.invalidate_lock);
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if (adev->flags & AMD_IS_APU) {
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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amdgpu_vm_adjust_size(adev, 64);
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} else {
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if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
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adev->vm_manager.vm_size = 1U << 18;
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adev->vm_manager.block_size = 9;
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adev->vm_manager.num_level = 3;
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} else {
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/* vm_size is 64GB for legacy 2-level page support*/
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amdgpu_vm_adjust_size(adev, 64);
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adev->vm_manager.num_level = 1;
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}
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break;
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case CHIP_VEGA10:
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/* XXX Don't know how to get VRAM type yet. */
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adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
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/*
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@ -550,11 +560,16 @@ static int gmc_v9_0_sw_init(void *handle)
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*/
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adev->vm_manager.vm_size = 1U << 18;
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adev->vm_manager.block_size = 9;
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DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
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adev->vm_manager.vm_size,
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adev->vm_manager.block_size);
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adev->vm_manager.num_level = 3;
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break;
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default:
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break;
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}
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DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
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adev->vm_manager.vm_size,
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adev->vm_manager.block_size);
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/* This interrupt is VMC page fault.*/
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r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
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&adev->mc.vm_fault);
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@ -619,11 +634,6 @@ static int gmc_v9_0_sw_init(void *handle)
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adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
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/* TODO: fix num_level for APU when updating vm size and block size */
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if (adev->flags & AMD_IS_APU)
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adev->vm_manager.num_level = 1;
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else
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adev->vm_manager.num_level = 3;
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amdgpu_vm_manager_init(adev);
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return 0;
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