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bpf, arm64: Optimize AND,OR,XOR,JSET BPF_K using arm64 logical immediates
The current code for BPF_{AND,OR,XOR,JSET} BPF_K loads the immediate to a temporary register before use. This patch changes the code to avoid using a temporary register when the BPF immediate is encodable using an arm64 logical immediate instruction. If the encoding fails (due to the immediate not being encodable), it falls back to using a temporary register. Example of generated code for BPF_ALU32_IMM(BPF_AND, R0, 0x80000001): without optimization: 24: mov w10, #0x8000ffff 28: movk w10, #0x1 2c: and w7, w7, w10 with optimization: 24: and w7, w7, #0x80000001 Since the encoding process is quite complex, the JIT reuses existing functionality in arch/arm64/kernel/insn.c for encoding logical immediates rather than duplicate it in the JIT. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/r/20200508181547.24783-3-luke.r.nels@gmail.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -189,4 +189,18 @@
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/* Rn & Rm; set condition flags */
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#define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
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/* Logical (immediate) */
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#define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \
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u64 imm64 = (sf) ? (u64)imm : (u64)(u32)imm; \
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aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_##type, \
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A64_VARIANT(sf), Rn, Rd, imm64); \
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})
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/* Rd = Rn OP imm */
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#define A64_AND_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND)
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#define A64_ORR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, ORR)
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#define A64_EOR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, EOR)
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#define A64_ANDS_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND_SETFLAGS)
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/* Rn & imm; set condition flags */
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#define A64_TST_I(sf, Rn, imm) A64_ANDS_I(sf, A64_ZR, Rn, imm)
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#endif /* _BPF_JIT_H */
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@ -356,6 +356,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
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const bool isdw = BPF_SIZE(code) == BPF_DW;
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u8 jmp_cond, reg;
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s32 jmp_offset;
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u32 a64_insn;
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#define check_imm(bits, imm) do { \
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if ((((imm) > 0) && ((imm) >> (bits))) || \
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@ -488,18 +489,33 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
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break;
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case BPF_ALU | BPF_AND | BPF_K:
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case BPF_ALU64 | BPF_AND | BPF_K:
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_AND(is64, dst, dst, tmp), ctx);
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a64_insn = A64_AND_I(is64, dst, dst, imm);
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if (a64_insn != AARCH64_BREAK_FAULT) {
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emit(a64_insn, ctx);
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} else {
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_AND(is64, dst, dst, tmp), ctx);
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}
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break;
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case BPF_ALU | BPF_OR | BPF_K:
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case BPF_ALU64 | BPF_OR | BPF_K:
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_ORR(is64, dst, dst, tmp), ctx);
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a64_insn = A64_ORR_I(is64, dst, dst, imm);
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if (a64_insn != AARCH64_BREAK_FAULT) {
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emit(a64_insn, ctx);
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} else {
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_ORR(is64, dst, dst, tmp), ctx);
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}
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break;
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case BPF_ALU | BPF_XOR | BPF_K:
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case BPF_ALU64 | BPF_XOR | BPF_K:
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_EOR(is64, dst, dst, tmp), ctx);
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a64_insn = A64_EOR_I(is64, dst, dst, imm);
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if (a64_insn != AARCH64_BREAK_FAULT) {
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emit(a64_insn, ctx);
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} else {
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_EOR(is64, dst, dst, tmp), ctx);
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}
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break;
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case BPF_ALU | BPF_MUL | BPF_K:
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case BPF_ALU64 | BPF_MUL | BPF_K:
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@ -628,8 +644,13 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
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goto emit_cond_jmp;
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case BPF_JMP | BPF_JSET | BPF_K:
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case BPF_JMP32 | BPF_JSET | BPF_K:
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_TST(is64, dst, tmp), ctx);
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a64_insn = A64_TST_I(is64, dst, imm);
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if (a64_insn != AARCH64_BREAK_FAULT) {
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emit(a64_insn, ctx);
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} else {
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emit_a64_mov_i(is64, tmp, imm, ctx);
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emit(A64_TST(is64, dst, tmp), ctx);
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}
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goto emit_cond_jmp;
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/* function call */
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case BPF_JMP | BPF_CALL:
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