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net: mvpp2: use the GoP interrupt for link status changes
This patch adds the GoP link interrupt support for when a port isn't connected to a PHY. Because of this the phylib callback is never called and the link status management isn't done. This patch use the GoP link interrupt in such cases to still have a minimal link management. Without this patch ports not connected to a PHY cannot work. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Antoine Tenart
David S. Miller
parent
5997c86bf0
commit
fd3651b2ab
@ -348,16 +348,24 @@
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#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
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#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVPP2_GMAC_STATUS0 0x10
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#define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
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#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
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MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
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#define MVPP22_GMAC_INT_STAT 0x20
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#define MVPP22_GMAC_INT_STAT_LINK BIT(1)
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#define MVPP22_GMAC_INT_MASK 0x24
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#define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1)
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#define MVPP22_GMAC_CTRL_4_REG 0x90
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#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
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#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
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#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)
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#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
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#define MVPP22_GMAC_INT_SUM_MASK 0xa4
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#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
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/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
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* relative to port->base.
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@ -370,11 +378,19 @@
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#define MVPP22_XLG_CTRL1_REG 0x104
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#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
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#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
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#define MVPP22_XLG_STATUS 0x10c
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#define MVPP22_XLG_STATUS_LINK_UP BIT(0)
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#define MVPP22_XLG_INT_STAT 0x114
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#define MVPP22_XLG_INT_STAT_LINK BIT(1)
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#define MVPP22_XLG_INT_MASK 0x118
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#define MVPP22_XLG_INT_MASK_LINK BIT(1)
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#define MVPP22_XLG_CTRL3_REG 0x11c
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#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
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#define MVPP22_XLG_EXT_INT_MASK 0x15c
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#define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)
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#define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)
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#define MVPP22_XLG_CTRL4_REG 0x184
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#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
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#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
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@ -837,6 +853,8 @@ struct mvpp2_port {
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*/
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int gop_id;
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int link_irq;
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struct mvpp2 *priv;
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/* Per-port registers' base address */
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@ -4422,6 +4440,68 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
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return -EINVAL;
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}
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static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
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{
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u32 val;
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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/* Enable the GMAC link status irq for this port */
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val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
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val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
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writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
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}
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if (port->gop_id == 0) {
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/* Enable the XLG/GIG irqs for this port */
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val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
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if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
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val |= MVPP22_XLG_EXT_INT_MASK_XLG;
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else
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val |= MVPP22_XLG_EXT_INT_MASK_GIG;
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writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
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}
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}
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static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
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{
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u32 val;
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if (port->gop_id == 0) {
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val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
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val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
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MVPP22_XLG_EXT_INT_MASK_GIG);
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writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
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}
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
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val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
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writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
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}
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}
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static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
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{
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u32 val;
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if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_INT_MASK);
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val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
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writel(val, port->base + MVPP22_GMAC_INT_MASK);
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}
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if (port->gop_id == 0) {
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val = readl(port->base + MVPP22_XLG_INT_MASK);
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val |= MVPP22_XLG_INT_MASK_LINK;
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writel(val, port->base + MVPP22_XLG_INT_MASK);
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}
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mvpp22_gop_unmask_irq(port);
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}
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static int mvpp22_comphy_init(struct mvpp2_port *port)
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{
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enum phy_mode mode;
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@ -5726,6 +5806,60 @@ static irqreturn_t mvpp2_isr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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/* Per-port interrupt for link status changes */
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static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
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{
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struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
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struct net_device *dev = port->dev;
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bool event = false, link = false;
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u32 val;
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mvpp22_gop_mask_irq(port);
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if (port->gop_id == 0 &&
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port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
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val = readl(port->base + MVPP22_XLG_INT_STAT);
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if (val & MVPP22_XLG_INT_STAT_LINK) {
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event = true;
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val = readl(port->base + MVPP22_XLG_STATUS);
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if (val & MVPP22_XLG_STATUS_LINK_UP)
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link = true;
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}
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} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
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port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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val = readl(port->base + MVPP22_GMAC_INT_STAT);
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if (val & MVPP22_GMAC_INT_STAT_LINK) {
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event = true;
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val = readl(port->base + MVPP2_GMAC_STATUS0);
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if (val & MVPP2_GMAC_STATUS0_LINK_UP)
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link = true;
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}
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}
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if (!netif_running(dev) || !event)
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goto handled;
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if (link) {
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mvpp2_interrupts_enable(port);
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mvpp2_egress_enable(port);
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mvpp2_ingress_enable(port);
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netif_carrier_on(dev);
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netif_tx_wake_all_queues(dev);
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} else {
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netif_tx_stop_all_queues(dev);
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netif_carrier_off(dev);
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mvpp2_ingress_disable(port);
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mvpp2_egress_disable(port);
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mvpp2_interrupts_disable(port);
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}
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handled:
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mvpp22_gop_unmask_irq(port);
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return IRQ_HANDLED;
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}
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static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,
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struct phy_device *phydev)
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{
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@ -5754,7 +5888,6 @@ static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,
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val |= MVPP2_GMAC_CONFIG_MII_SPEED;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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/* Adjust link */
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@ -6633,6 +6766,7 @@ static void mvpp2_irqs_deinit(struct mvpp2_port *port)
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static int mvpp2_open(struct net_device *dev)
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{
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struct mvpp2_port *port = netdev_priv(dev);
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struct mvpp2 *priv = port->priv;
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unsigned char mac_bcast[ETH_ALEN] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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int err;
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@ -6678,12 +6812,24 @@ static int mvpp2_open(struct net_device *dev)
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goto err_cleanup_txqs;
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}
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if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) {
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err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
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dev->name, port);
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if (err) {
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netdev_err(port->dev, "cannot request link IRQ %d\n",
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port->link_irq);
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goto err_free_irq;
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}
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mvpp22_gop_setup_irq(port);
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}
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/* In default link is down */
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netif_carrier_off(port->dev);
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err = mvpp2_phy_connect(port);
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if (err < 0)
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goto err_free_irq;
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goto err_free_link_irq;
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/* Unmask interrupts on all CPUs */
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on_each_cpu(mvpp2_interrupts_unmask, port, 1);
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@ -6693,6 +6839,9 @@ static int mvpp2_open(struct net_device *dev)
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return 0;
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err_free_link_irq:
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if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)
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free_irq(port->link_irq, port);
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err_free_irq:
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mvpp2_irqs_deinit(port);
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err_cleanup_txqs:
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@ -6706,6 +6855,7 @@ static int mvpp2_stop(struct net_device *dev)
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{
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struct mvpp2_port *port = netdev_priv(dev);
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struct mvpp2_port_pcpu *port_pcpu;
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struct mvpp2 *priv = port->priv;
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int cpu;
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mvpp2_stop_dev(port);
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@ -6715,6 +6865,9 @@ static int mvpp2_stop(struct net_device *dev)
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on_each_cpu(mvpp2_interrupts_mask, port, 1);
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mvpp2_shared_interrupt_mask_unmask(port, true);
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if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)
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free_irq(port->link_irq, port);
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mvpp2_irqs_deinit(port);
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if (!port->has_tx_irqs) {
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for_each_present_cpu(cpu) {
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@ -7387,6 +7540,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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if (err)
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goto err_free_netdev;
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port->link_irq = of_irq_get_byname(port_node, "link");
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if (port->link_irq == -EPROBE_DEFER) {
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err = -EPROBE_DEFER;
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goto err_deinit_qvecs;
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}
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if (port->link_irq <= 0)
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/* the link irq is optional */
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port->link_irq = 0;
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if (of_property_read_bool(port_node, "marvell,loopback"))
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port->flags |= MVPP2_F_LOOPBACK;
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@ -7405,7 +7567,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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port->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(port->base)) {
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err = PTR_ERR(port->base);
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goto err_deinit_qvecs;
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goto err_free_irq;
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}
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} else {
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if (of_property_read_u32(port_node, "gop-port-id",
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@ -7422,7 +7584,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
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if (!port->stats) {
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err = -ENOMEM;
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goto err_deinit_qvecs;
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goto err_free_irq;
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}
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dt_mac_addr = of_get_mac_address(port_node);
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@ -7506,6 +7668,9 @@ static int mvpp2_port_probe(struct platform_device *pdev,
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free_percpu(port->txqs[i]->pcpu);
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err_free_stats:
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free_percpu(port->stats);
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err_free_irq:
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if (port->link_irq)
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irq_dispose_mapping(port->link_irq);
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err_deinit_qvecs:
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mvpp2_queue_vectors_deinit(port);
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err_free_netdev:
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@ -7526,6 +7691,8 @@ static void mvpp2_port_remove(struct mvpp2_port *port)
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for (i = 0; i < port->ntxqs; i++)
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free_percpu(port->txqs[i]->pcpu);
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mvpp2_queue_vectors_deinit(port);
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if (port->link_irq)
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irq_dispose_mapping(port->link_irq);
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free_netdev(port->dev);
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}
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