AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-26 12:20:50 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge branch 'fbdev/panning-fixes'

Browse Source
This commit is contained in:
Paul Mundt 2011-06-15 15:48:40 +09:00
commit fc90ec8629
345 changed files with 3313 additions and 1517 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/md.txt
View File

@ -555,7 +555,7 @@ also have
sync_min
sync_max
The two values, given as numbers of sectors, indicate a range
withing the array where 'check'/'repair' will operate. Must be
within the array where 'check'/'repair' will operate. Must be
a multiple of chunk_size. When it reaches "sync_max" it will
pause, rather than complete.
You can use 'select' or 'poll' on "sync_completed" to wait for

4
MAINTAINERS
View File

@ -1739,7 +1739,7 @@ S: Supported
F: drivers/net/enic/
CIRRUS LOGIC EP93XX ETHERNET DRIVER
M: Lennert Buytenhek <kernel@wantstofly.org>
M: Hartley Sweeten <hsweeten@visionengravers.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/arm/ep93xx_eth.c
@ -1889,7 +1889,6 @@ L: cpufreq@vger.kernel.org
W: http://www.codemonkey.org.uk/projects/cpufreq/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git
S: Maintained
F: arch/x86/kernel/cpu/cpufreq/
F: drivers/cpufreq/
F: include/linux/cpufreq.h
@ -4945,6 +4944,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/epip/linux-2.6-unicore32.gi
F: drivers/input/serio/i8042-unicore32io.h
F: drivers/i2c/busses/i2c-puv3.c
F: drivers/video/fb-puv3.c
F: drivers/rtc/rtc-puv3.c
PMC SIERRA MaxRAID DRIVER
M: Anil Ravindranath <anil_ravindranath@pmc-sierra.com>

18
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 0
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME = Sneaky Weasel
# *DOCUMENTATION*
@ -378,7 +378,7 @@ KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds
# Read KERNELRELEASE from include/config/kernel.release (if it exists)
KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null)
KERNELVERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
KERNELVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION
export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC
@ -1005,7 +1005,7 @@ endef
define filechk_version.h
(echo \#define LINUX_VERSION_CODE $(shell \
expr $(VERSION) \* 65536 + $(PATCHLEVEL) \* 256 + $(SUBLEVEL)); \
expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 0$(SUBLEVEL)); \
echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))';)
endef
@ -1110,11 +1110,6 @@ modules_install: _modinst_ _modinst_post
PHONY += _modinst_
_modinst_:
@if [ -z "`$(DEPMOD) -V 2>/dev/null | grep module-init-tools`" ]; then \
echo "Warning: you may need to install module-init-tools"; \
echo "See http://www.codemonkey.org.uk/docs/post-halloween-2.6.txt";\
sleep 1; \
fi
@rm -rf $(MODLIB)/kernel
@rm -f $(MODLIB)/source
@mkdir -p $(MODLIB)/kernel
@ -1531,12 +1526,7 @@ quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))
# Run depmod only if we have System.map and depmod is executable
quiet_cmd_depmod = DEPMOD $(KERNELRELEASE)
cmd_depmod = \
if [ -r System.map -a -x $(DEPMOD) ]; then \
$(DEPMOD) -ae -F System.map \
$(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) ) \
$(KERNELRELEASE); \
fi
cmd_depmod = $(srctree)/scripts/depmod.sh $(DEPMOD) $(KERNELRELEASE)
# Create temporary dir for module support files
# clean it up only when building all modules

4
arch/arm/mach-ep93xx/core.c
View File

@ -402,11 +402,15 @@ static struct resource ep93xx_eth_resource[] = {
}
};
static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
static struct platform_device ep93xx_eth_device = {
.name = "ep93xx-eth",
.id = -1,
.dev = {
.platform_data = &ep93xx_eth_data,
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &ep93xx_eth_dma_mask,
},
.num_resources = ARRAY_SIZE(ep93xx_eth_resource),
.resource = ep93xx_eth_resource,

6
arch/arm/mach-exynos4/Kconfig
View File

@ -91,6 +91,11 @@ config EXYNOS4_SETUP_FIMC
help
Common setup code for the camera interfaces.
config EXYNOS4_SETUP_USB_PHY
bool
help
Common setup code for USB PHY controller
# machine support
menu "EXYNOS4 Machines"
@ -176,6 +181,7 @@ config MACH_NURI
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM
help
Machine support for Samsung Mobile NURI Board.

2
arch/arm/mach-exynos4/Makefile
View File

@ -56,4 +56,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_USB_SUPPORT) += usb-phy.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o

2
arch/arm/mach-exynos4/cpu.c
View File

@ -98,7 +98,7 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_USB_HSPHY,
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,

2
arch/arm/mach-exynos4/include/mach/regs-usb-phy.h
View File

@ -11,7 +11,7 @@
#ifndef __PLAT_S5P_REGS_USB_PHY_H
#define __PLAT_S5P_REGS_USB_PHY_H
#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S5P_VA_USB_HSPHY)
#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
#define PHY1_HSIC_NORMAL_MASK (0xf << 9)

0
arch/arm/mach-exynos4/usb-phy.c → arch/arm/mach-exynos4/setup-usb-phy.c
View File

2
arch/arm/mach-exynos4/time.c
View File

@ -206,6 +206,7 @@ static cycle_t exynos4_pwm4_read(struct clocksource *cs)
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
}
#ifdef CONFIG_PM
static void exynos4_pwm4_resume(struct clocksource *cs)
{
unsigned long pclk;
@ -218,6 +219,7 @@ static void exynos4_pwm4_resume(struct clocksource *cs)
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
}
#endif
struct clocksource pwm_clocksource = {
.name = "pwm_timer4",

1
arch/arm/mach-s3c2410/Makefile
View File

@ -10,7 +10,6 @@ obj-n :=
obj- :=
obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
obj-$(CONFIG_CPU_S3C2410) += irq.o
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o

34
arch/arm/mach-s3c2410/irq.c
View File

@ -1,34 +0,0 @@
/* linux/arch/arm/mach-s3c2410/irq.c
*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/syscore_ops.h>
#include <plat/cpu.h>
#include <plat/pm.h>
struct syscore_ops s3c24xx_irq_syscore_ops = {
.suspend = s3c24xx_irq_suspend,
.resume = s3c24xx_irq_resume,
};

8
arch/arm/mach-s5pv210/cpufreq.c
View File

@ -101,12 +101,14 @@ static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
unsigned long tmp, tmp1;
void __iomem *reg = NULL;
if (ch == DMC0)
if (ch == DMC0) {
reg = (S5P_VA_DMC0 + 0x30);
else if (ch == DMC1)
} else if (ch == DMC1) {
reg = (S5P_VA_DMC1 + 0x30);
else
} else {
printk(KERN_ERR "Cannot find DMC port\n");
return;
}
/* Find current DRAM frequency */
tmp = s5pv210_dram_conf[ch].freq;

3
arch/arm/mach-ux500/cpu-db8500.c
View File

@ -159,6 +159,9 @@ static void __init db8500_add_gpios(void)
/* No custom data yet */
};
if (cpu_is_u8500v2())
pdata.supports_sleepmode = true;
dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
IRQ_DB8500_GPIO0, &pdata);
}

1
arch/arm/plat-nomadik/include/plat/gpio.h
View File

@ -90,6 +90,7 @@ struct nmk_gpio_platform_data {
int num_gpio;
u32 (*get_secondary_status)(unsigned int bank);
void (*set_ioforce)(bool enable);
bool supports_sleepmode;
};
#endif /* __ASM_PLAT_GPIO_H */

2
arch/arm/plat-s3c24xx/dma.c
View File

@ -1199,7 +1199,7 @@ EXPORT_SYMBOL(s3c2410_dma_getposition);
#ifdef CONFIG_PM
static void s3c2410_dma_suspend_chan(s3c2410_dma_chan *cp)
static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan *cp)
{
printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);

6
arch/arm/plat-s3c24xx/irq.c
View File

@ -23,6 +23,7 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>
#include <linux/syscore_ops.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
@ -668,3 +669,8 @@ void __init s3c24xx_init_irq(void)
irqdbf("s3c2410: registered interrupt handlers\n");
}
struct syscore_ops s3c24xx_irq_syscore_ops = {
.suspend = s3c24xx_irq_suspend,
.resume = s3c24xx_irq_resume,
};

12
arch/arm/plat-s5p/dev-onenand.c
View File

@ -15,8 +15,6 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <mach/irqs.h>
#include <mach/map.h>
@ -45,13 +43,3 @@ struct platform_device s5p_device_onenand = {
.num_resources = ARRAY_SIZE(s5p_onenand_resources),
.resource = s5p_onenand_resources,
};
void s5p_onenand_set_platdata(struct onenand_platform_data *pdata)
{
struct onenand_platform_data *pd;
pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
if (!pd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s5p_device_onenand.dev.platform_data = pd;
}

2
arch/arm/plat-s5p/include/plat/map-s5p.h
View File

@ -39,7 +39,7 @@
#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
#define S5P_VA_USB_HSPHY S3C_ADDR(0x02900000)
#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
#define VA_VIC0 VA_VIC(0)

12
arch/arm/plat-samsung/dev-onenand.c
View File

@ -13,8 +13,6 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <mach/irqs.h>
#include <mach/map.h>
@ -43,13 +41,3 @@ struct platform_device s3c_device_onenand = {
.num_resources = ARRAY_SIZE(s3c_onenand_resources),
.resource = s3c_onenand_resources,
};
void s3c_onenand_set_platdata(struct onenand_platform_data *pdata)
{
struct onenand_platform_data *pd;
pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
if (!pd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s3c_device_onenand.dev.platform_data = pd;
}

6
arch/arm/plat-samsung/include/plat/devs.h
View File

@ -75,10 +75,8 @@ extern struct platform_device s5pc100_device_spi1;
extern struct platform_device s5pc100_device_spi2;
extern struct platform_device s5pv210_device_spi0;
extern struct platform_device s5pv210_device_spi1;
extern struct platform_device s5p6440_device_spi0;
extern struct platform_device s5p6440_device_spi1;
extern struct platform_device s5p6450_device_spi0;
extern struct platform_device s5p6450_device_spi1;
extern struct platform_device s5p64x0_device_spi0;
extern struct platform_device s5p64x0_device_spi1;
extern struct platform_device s3c_device_hwmon;

1
arch/avr32/configs/atngw100_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atngw100_evklcd100_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atngw100_evklcd101_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atngw100_mrmt_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_SLUB_DEBUG is not set

1
arch/avr32/configs/atngw100mkii_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atngw100mkii_evklcd100_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atngw100mkii_evklcd101_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atstk1002_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atstk1003_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atstk1004_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/atstk1006_defconfig
View File

@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/favr-32_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/hammerhead_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/configs/merisc_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
CONFIG_MODULES=y

1
arch/avr32/configs/mimc200_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_BASE_FULL is not set
# CONFIG_COMPAT_BRK is not set

1
arch/avr32/include/asm/processor.h
View File

@ -131,7 +131,6 @@ struct thread_struct {
*/
#define start_thread(regs, new_pc, new_sp) \
do { \
set_fs(USER_DS); \
memset(regs, 0, sizeof(*regs)); \
regs->sr = MODE_USER; \
regs->pc = new_pc & ~1; \

3
arch/avr32/mach-at32ap/at32ap700x.c
View File

@ -1043,8 +1043,9 @@ void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
data->regs = (void __iomem *)pdev->resource[0].start;
}
pdev->id = line;
pdata = pdev->dev.platform_data;
pdata->num = portnr;
pdata->num = line;
at32_usarts[line] = pdev;
}

12
arch/avr32/mach-at32ap/include/mach/cpu.h
View File

@ -31,8 +31,20 @@
#define cpu_is_at91sam9263() (0)
#define cpu_is_at91sam9rl() (0)
#define cpu_is_at91cap9() (0)
#define cpu_is_at91cap9_revB() (0)
#define cpu_is_at91cap9_revC() (0)
#define cpu_is_at91sam9g10() (0)
#define cpu_is_at91sam9g20() (0)
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
#define cpu_is_at91sam9m10() (0)
#define cpu_is_at91sam9g46() (0)
#define cpu_is_at91sam9m11() (0)
#define cpu_is_at91sam9x5() (0)
#define cpu_is_at91sam9g15() (0)
#define cpu_is_at91sam9g35() (0)
#define cpu_is_at91sam9x35() (0)
#define cpu_is_at91sam9g25() (0)
#define cpu_is_at91sam9x25() (0)
#endif /* __ASM_ARCH_CPU_H */

4
arch/avr32/mach-at32ap/intc.c
View File

@ -167,14 +167,12 @@ static int intc_suspend(void)
return 0;
}
static int intc_resume(void)
static void intc_resume(void)
{
int i;
for (i = 0; i < 64; i++)
intc_writel(&intc0, INTPR0 + 4 * i, intc0.saved_ipr[i]);
return 0;
}
#else
#define intc_suspend NULL

52
arch/m68k/Kconfig.nommu
View File

@ -14,6 +14,33 @@ config GENERIC_CLOCKEVENTS
bool
default n
config M68000
bool
help
The Freescale (was Motorola) 68000 CPU is the first generation of
the well known M68K family of processors. The CPU core as well as
being available as a stand alone CPU was also used in many
System-On-Chip devices (eg 68328, 68302, etc). It does not contain
a paging MMU.
config MCPU32
bool
help
The Freescale (was then Motorola) CPU32 is a CPU core that is
based on the 68020 processor. For the most part it is used in
System-On-Chip parts, and does not contain a paging MMU.
config COLDFIRE
bool
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
help
The Freescale ColdFire family of processors is a modern derivitive
of the 68000 processor family. They are mainly targeted at embedded
applications, and are all System-On-Chip (SOC) devices, as opposed
to stand alone CPUs. They implement a subset of the original 68000
processor instruction set.
config COLDFIRE_SW_A7
bool
default n
@ -36,26 +63,31 @@ choice
config M68328
bool "MC68328"
select M68000
help
Motorola 68328 processor support.
config M68EZ328
bool "MC68EZ328"
select M68000
help
Motorola 68EX328 processor support.
config M68VZ328
bool "MC68VZ328"
select M68000
help
Motorola 68VZ328 processor support.
config M68360
bool "MC68360"
select MCPU32
help
Motorola 68360 processor support.
config M5206
bool "MCF5206"
select COLDFIRE
select COLDFIRE_SW_A7
select HAVE_MBAR
help
@ -63,6 +95,7 @@ config M5206
config M5206e
bool "MCF5206e"
select COLDFIRE
select COLDFIRE_SW_A7
select HAVE_MBAR
help
@ -70,6 +103,7 @@ config M5206e
config M520x
bool "MCF520x"
select COLDFIRE
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
help
@ -77,6 +111,7 @@ config M520x
config M523x
bool "MCF523x"
select COLDFIRE
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
@ -85,6 +120,7 @@ config M523x
config M5249
bool "MCF5249"
select COLDFIRE
select COLDFIRE_SW_A7
select HAVE_MBAR
help
@ -92,6 +128,7 @@ config M5249
config M5271
bool "MCF5271"
select COLDFIRE
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
help
@ -99,6 +136,7 @@ config M5271
config M5272
bool "MCF5272"
select COLDFIRE
select COLDFIRE_SW_A7
select HAVE_MBAR
help
@ -106,6 +144,7 @@ config M5272
config M5275
bool "MCF5275"
select COLDFIRE
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
help
@ -113,6 +152,7 @@ config M5275
config M528x
bool "MCF528x"
select COLDFIRE
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
@ -121,6 +161,7 @@ config M528x
config M5307
bool "MCF5307"
select COLDFIRE
select COLDFIRE_SW_A7
select HAVE_CACHE_CB
select HAVE_MBAR
@ -129,12 +170,14 @@ config M5307
config M532x
bool "MCF532x"
select COLDFIRE
select HAVE_CACHE_CB
help
Freescale (Motorola) ColdFire 532x processor support.
config M5407
bool "MCF5407"
select COLDFIRE
select COLDFIRE_SW_A7
select HAVE_CACHE_CB
select HAVE_MBAR
@ -143,6 +186,7 @@ config M5407
config M547x
bool "MCF547x"
select COLDFIRE
select HAVE_CACHE_CB
select HAVE_MBAR
help
@ -150,6 +194,7 @@ config M547x
config M548x
bool "MCF548x"
select COLDFIRE
select HAVE_CACHE_CB
select HAVE_MBAR
help
@ -168,13 +213,6 @@ config M54xx
depends on (M548x || M547x)
default y
config COLDFIRE
bool
depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx)
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
default y
config CLOCK_SET
bool "Enable setting the CPU clock frequency"
default n

3
arch/m68k/kernel/m68k_ksyms.c
View File

@ -14,8 +14,7 @@ EXPORT_SYMBOL(__ashrdi3);
EXPORT_SYMBOL(__lshrdi3);
EXPORT_SYMBOL(__muldi3);
#if !defined(__mc68020__) && !defined(__mc68030__) && \
!defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcpu32__)
#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
/*
* Simpler 68k and ColdFire parts also need a few other gcc functions.
*/

20
arch/m68k/kernel/vmlinux.lds_no.S
View File

@ -84,52 +84,52 @@ SECTIONS {
/* Kernel symbol table: Normal symbols */
. = ALIGN(4);
__start___ksymtab = .;
*(__ksymtab)
*(SORT(___ksymtab+*))
__stop___ksymtab = .;
/* Kernel symbol table: GPL-only symbols */
__start___ksymtab_gpl = .;
*(__ksymtab_gpl)
*(SORT(___ksymtab_gpl+*))
__stop___ksymtab_gpl = .;
/* Kernel symbol table: Normal unused symbols */
__start___ksymtab_unused = .;
*(__ksymtab_unused)
*(SORT(___ksymtab_unused+*))
__stop___ksymtab_unused = .;
/* Kernel symbol table: GPL-only unused symbols */
__start___ksymtab_unused_gpl = .;
*(__ksymtab_unused_gpl)
*(SORT(___ksymtab_unused_gpl+*))
__stop___ksymtab_unused_gpl = .;
/* Kernel symbol table: GPL-future symbols */
__start___ksymtab_gpl_future = .;
*(__ksymtab_gpl_future)
*(SORT(___ksymtab_gpl_future+*))
__stop___ksymtab_gpl_future = .;
/* Kernel symbol table: Normal symbols */
__start___kcrctab = .;
*(__kcrctab)
*(SORT(___kcrctab+*))
__stop___kcrctab = .;
/* Kernel symbol table: GPL-only symbols */
__start___kcrctab_gpl = .;
*(__kcrctab_gpl)
*(SORT(___kcrctab_gpl+*))
__stop___kcrctab_gpl = .;
/* Kernel symbol table: Normal unused symbols */
__start___kcrctab_unused = .;
*(__kcrctab_unused)
*(SORT(___kcrctab_unused+*))
__stop___kcrctab_unused = .;
/* Kernel symbol table: GPL-only unused symbols */
__start___kcrctab_unused_gpl = .;
*(__kcrctab_unused_gpl)
*(SORT(___kcrctab_unused_gpl+*))
__stop___kcrctab_unused_gpl = .;
/* Kernel symbol table: GPL-future symbols */
__start___kcrctab_gpl_future = .;
*(__kcrctab_gpl_future)
*(SORT(___kcrctab_gpl_future+*))
__stop___kcrctab_gpl_future = .;
/* Kernel symbol table: strings */

9
arch/m68k/lib/memcpy.c
View File

@ -34,8 +34,10 @@ void *memcpy(void *to, const void *from, size_t n)
if (temp) {
long *lto = to;
const long *lfrom = from;
#if defined(__mc68020__) || defined(__mc68030__) || \
defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
for (; temp; temp--)
*lto++ = *lfrom++;
#else
asm volatile (
" movel %2,%3\n"
" andw #7,%3\n"
@ -56,9 +58,6 @@ void *memcpy(void *to, const void *from, size_t n)
" jpl 4b"
: "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1)
: "0" (lfrom), "1" (lto), "2" (temp));
#else
for (; temp; temp--)
*lto++ = *lfrom++;
#endif
to = lto;
from = lfrom;

9
arch/m68k/lib/memset.c
View File

@ -32,8 +32,10 @@ void *memset(void *s, int c, size_t count)
temp = count >> 2;
if (temp) {
long *ls = s;
#if defined(__mc68020__) || defined(__mc68030__) || \
defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
for (; temp; temp--)
*ls++ = c;
#else
size_t temp1;
asm volatile (
" movel %1,%2\n"
@ -55,9 +57,6 @@ void *memset(void *s, int c, size_t count)
" jpl 1b"
: "=a" (ls), "=d" (temp), "=&d" (temp1)
: "d" (c), "0" (ls), "1" (temp));
#else
for (; temp; temp--)
*ls++ = c;
#endif
s = ls;
}

21
arch/m68k/lib/muldi3.c
View File

@ -19,17 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#if defined(__mc68020__) || defined(__mc68030__) || \
defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
: "=d" ((USItype)(w0)), \
"=d" ((USItype)(w1)) \
: "%0" ((USItype)(u)), \
"dmi" ((USItype)(v)))
#else
#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
#define SI_TYPE_SIZE 32
#define __BITS4 (SI_TYPE_SIZE / 4)
@ -61,6 +51,15 @@ Boston, MA 02111-1307, USA. */
(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
} while (0)
#else
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
: "=d" ((USItype)(w0)), \
"=d" ((USItype)(w1)) \
: "%0" ((USItype)(u)), \
"dmi" ((USItype)(v)))
#endif
#define __umulsidi3(u, v) \

1
arch/powerpc/boot/.gitignore vendored
View File

@ -1,5 +1,4 @@
addnote
dtc
empty.c
hack-coff
infblock.c

3
arch/powerpc/boot/dtc-src/.gitignore vendored
View File

@ -1,3 +0,0 @@
dtc-lexer.lex.c
dtc-parser.tab.c
dtc-parser.tab.h

2
arch/powerpc/include/asm/rio.h
View File

@ -14,7 +14,7 @@
#define ASM_PPC_RIO_H
extern void platform_rio_init(void);
#ifdef CONFIG_RAPIDIO
#ifdef CONFIG_FSL_RIO
extern int fsl_rio_mcheck_exception(struct pt_regs *);
#else
static inline int fsl_rio_mcheck_exception(struct pt_regs *regs) {return 0; }

2
arch/powerpc/kernel/cputable.c
View File

@ -1979,7 +1979,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.pvr_value = 0x80240000,
.cpu_name = "e5500",
.cpu_features = CPU_FTRS_E5500,
.cpu_user_features = COMMON_USER_BOOKE,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,

27
arch/powerpc/kernel/prom.c
View File

@ -82,11 +82,29 @@ static int __init early_parse_mem(char *p)
}
early_param("mem", early_parse_mem);
/*
* overlaps_initrd - check for overlap with page aligned extension of
* initrd.
*/
static inline int overlaps_initrd(unsigned long start, unsigned long size)
{
#ifdef CONFIG_BLK_DEV_INITRD
if (!initrd_start)
return 0;
return (start + size) > _ALIGN_DOWN(initrd_start, PAGE_SIZE) &&
start <= _ALIGN_UP(initrd_end, PAGE_SIZE);
#else
return 0;
#endif
}
/**
* move_device_tree - move tree to an unused area, if needed.
*
* The device tree may be allocated beyond our memory limit, or inside the
* crash kernel region for kdump. If so, move it out of the way.
* crash kernel region for kdump, or within the page aligned range of initrd.
* If so, move it out of the way.
*/
static void __init move_device_tree(void)
{
@ -99,7 +117,8 @@ static void __init move_device_tree(void)
size = be32_to_cpu(initial_boot_params->totalsize);
if ((memory_limit && (start + size) > PHYSICAL_START + memory_limit) ||
overlaps_crashkernel(start, size)) {
overlaps_crashkernel(start, size) ||
overlaps_initrd(start, size)) {
p = __va(memblock_alloc(size, PAGE_SIZE));
memcpy(p, initial_boot_params, size);
initial_boot_params = (struct boot_param_header *)p;
@ -555,7 +574,9 @@ static void __init early_reserve_mem(void)
#ifdef CONFIG_BLK_DEV_INITRD
/* then reserve the initrd, if any */
if (initrd_start && (initrd_end > initrd_start))
memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
memblock_reserve(_ALIGN_DOWN(__pa(initrd_start), PAGE_SIZE),
_ALIGN_UP(initrd_end, PAGE_SIZE) -
_ALIGN_DOWN(initrd_start, PAGE_SIZE));
#endif /* CONFIG_BLK_DEV_INITRD */
#ifdef CONFIG_PPC32

15
arch/powerpc/mm/init_32.c
View File

@ -223,21 +223,6 @@ void free_initmem(void)
#undef FREESEC
}
#ifdef CONFIG_BLK_DEV_INITRD
void free_initrd_mem(unsigned long start, unsigned long end)
{
if (start < end)
printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
for (; start < end; start += PAGE_SIZE) {
ClearPageReserved(virt_to_page(start));
init_page_count(virt_to_page(start));
free_page(start);
totalram_pages++;
}
}
#endif
#ifdef CONFIG_8xx /* No 8xx specific .c file to put that in ... */
void setup_initial_memory_limit(phys_addr_t first_memblock_base,
phys_addr_t first_memblock_size)

14
arch/powerpc/mm/init_64.c
View File

@ -99,20 +99,6 @@ void free_initmem(void)
((unsigned long)__init_end - (unsigned long)__init_begin) >> 10);
}
#ifdef CONFIG_BLK_DEV_INITRD
void free_initrd_mem(unsigned long start, unsigned long end)
{
if (start < end)
printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
for (; start < end; start += PAGE_SIZE) {
ClearPageReserved(virt_to_page(start));
init_page_count(virt_to_page(start));
free_page(start);
totalram_pages++;
}
}
#endif
static void pgd_ctor(void *addr)
{
memset(addr, 0, PGD_TABLE_SIZE);

19
arch/powerpc/mm/mem.c
View File

@ -382,6 +382,25 @@ void __init mem_init(void)
mem_init_done = 1;
}
#ifdef CONFIG_BLK_DEV_INITRD
void __init free_initrd_mem(unsigned long start, unsigned long end)
{
if (start >= end)
return;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
pr_info("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
for (; start < end; start += PAGE_SIZE) {
ClearPageReserved(virt_to_page(start));
init_page_count(virt_to_page(start));
free_page(start);
totalram_pages++;
}
}
#endif
/*
* This is called when a page has been modified by the kernel.
* It just marks the page as not i-cache clean. We do the i-cache

6
arch/powerpc/sysdev/fsl_lbc.c
View File

@ -196,9 +196,6 @@ static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
out_be32(&lbc->lteccr, LTECCR_CLEAR);
out_be32(&lbc->ltedr, LTEDR_ENABLE);
/* Enable interrupts for any detected events */
out_be32(&lbc->lteir, LTEIR_ENABLE);
/* Set the monitor timeout value to the maximum for erratum A001 */
if (of_device_is_compatible(node, "fsl,elbc"))
clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
@ -322,6 +319,9 @@ static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
goto err;
}
/* Enable interrupts for any detected events */
out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
return 0;
err:

18
arch/sparc/Kconfig
View File

@ -26,7 +26,6 @@ config SPARC
select HAVE_DMA_API_DEBUG
select HAVE_ARCH_JUMP_LABEL
select HAVE_GENERIC_HARDIRQS
select GENERIC_HARDIRQS_NO_DEPRECATED
select GENERIC_IRQ_SHOW
select USE_GENERIC_SMP_HELPERS if SMP
@ -528,6 +527,23 @@ config PCI_DOMAINS
config PCI_SYSCALL
def_bool PCI
config PCIC_PCI
bool
depends on PCI && SPARC32 && !SPARC_LEON
default y
config LEON_PCI
bool
depends on PCI && SPARC_LEON
default y
config GRPCI2
bool "GRPCI2 Host Bridge Support"
depends on LEON_PCI
default y
help
Say Y here to include the GRPCI2 Host Bridge Driver.
source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"

8
arch/sparc/include/asm/floppy_32.h
View File

@ -138,7 +138,7 @@ static unsigned char sun_82072_fd_inb(int port)
return sun_fdc->data_82072;
case 7: /* FD_DIR */
return sun_read_dir();
};
}
panic("sun_82072_fd_inb: How did I get here?");
}
@ -161,7 +161,7 @@ static void sun_82072_fd_outb(unsigned char value, int port)
case 4: /* FD_STATUS */
sun_fdc->status_82072 = value;
break;
};
}
return;
}
@ -186,7 +186,7 @@ static unsigned char sun_82077_fd_inb(int port)
return sun_fdc->data_82077;
case 7: /* FD_DIR */
return sun_read_dir();
};
}
panic("sun_82077_fd_inb: How did I get here?");
}
@ -212,7 +212,7 @@ static void sun_82077_fd_outb(unsigned char value, int port)
case 3: /* FD_TDR */
sun_fdc->tapectl_82077 = value;
break;
};
}
return;
}

4
arch/sparc/include/asm/floppy_64.h
View File

@ -111,7 +111,7 @@ static unsigned char sun_82077_fd_inb(unsigned long port)
case 7: /* FD_DIR */
/* XXX: Is DCL on 0x80 in sun4m? */
return sbus_readb(&sun_fdc->dir_82077);
};
}
panic("sun_82072_fd_inb: How did I get here?");
}
@ -135,7 +135,7 @@ static void sun_82077_fd_outb(unsigned char value, unsigned long port)
case 4: /* FD_STATUS */
sbus_writeb(value, &sun_fdc->status_82077);
break;
};
}
return;
}

3
arch/sparc/include/asm/leon.h
View File

@ -318,6 +318,9 @@ struct device_node;
extern unsigned int leon_build_device_irq(unsigned int real_irq,
irq_flow_handler_t flow_handler,
const char *name, int do_ack);
extern void leon_update_virq_handling(unsigned int virq,
irq_flow_handler_t flow_handler,
const char *name, int do_ack);
extern void leon_clear_clock_irq(void);
extern void leon_load_profile_irq(int cpu, unsigned int limit);
extern void leon_init_timers(irq_handler_t counter_fn);

21
arch/sparc/include/asm/leon_pci.h Normal file
View File

@ -0,0 +1,21 @@
/*
* asm/leon_pci.h
*
* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
*/
#ifndef _ASM_LEON_PCI_H_
#define _ASM_LEON_PCI_H_
/* PCI related definitions */
struct leon_pci_info {
struct pci_ops *ops;
struct resource io_space;
struct resource mem_space;
int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
};
extern void leon_pci_init(struct platform_device *ofdev,
struct leon_pci_info *info);
#endif /* _ASM_LEON_PCI_H_ */

24
arch/sparc/include/asm/pci_32.h
View File

@ -47,7 +47,31 @@ extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
#endif /* __KERNEL__ */
#ifndef CONFIG_LEON_PCI
/* generic pci stuff */
#include <asm-generic/pci.h>
#else
/*
* On LEON PCI Memory space is mapped 1:1 with physical address space.
*
* I/O space is located at low 64Kbytes in PCI I/O space. The I/O addresses
* are converted into CPU addresses to virtual addresses that are mapped with
* MMU to the PCI Host PCI I/O space window which are translated to the low
* 64Kbytes by the Host controller.
*/
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res);
extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
return PCI_IRQ_NONE;
}
#endif
#endif /* __SPARC_PCI_H */

2
arch/sparc/include/asm/pcic.h
View File

@ -29,7 +29,7 @@ struct linux_pcic {
int pcic_imdim;
};
#ifdef CONFIG_PCI
#ifdef CONFIG_PCIC_PCI
extern int pcic_present(void);
extern int pcic_probe(void);
extern void pci_time_init(void);

2
arch/sparc/include/asm/system_32.h
View File

@ -220,7 +220,7 @@ static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int
switch (size) {
case 4:
return xchg_u32(ptr, x);
};
}
__xchg_called_with_bad_pointer();
return x;
}

2
arch/sparc/include/asm/system_64.h
View File

@ -234,7 +234,7 @@ static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
return xchg32(ptr, x);
case 8:
return xchg64(ptr, x);
};
}
__xchg_called_with_bad_pointer();
return x;
}

4
arch/sparc/kernel/Makefile
View File

@ -73,7 +73,9 @@ obj-$(CONFIG_SPARC64_SMP) += cpumap.o
obj-y += dma.o
obj-$(CONFIG_SPARC32_PCI) += pcic.o
obj-$(CONFIG_PCIC_PCI) += pcic.o
obj-$(CONFIG_LEON_PCI) += leon_pci.o
obj-$(CONFIG_GRPCI2) += leon_pci_grpci2.o
obj-$(CONFIG_SMP) += trampoline_$(BITS).o smp_$(BITS).o
obj-$(CONFIG_SPARC32_SMP) += sun4m_smp.o sun4d_smp.o leon_smp.o

2
arch/sparc/kernel/apc.c
View File

@ -123,7 +123,7 @@ static long apc_ioctl(struct file *f, unsigned int cmd, unsigned long __arg)
default:
return -EINVAL;
};
}
return 0;
}

2
arch/sparc/kernel/auxio_32.c
View File

@ -101,7 +101,7 @@ void set_auxio(unsigned char bits_on, unsigned char bits_off)
break;
default:
panic("Can't set AUXIO register on this machine.");
};
}
spin_unlock_irqrestore(&auxio_lock, flags);
}
EXPORT_SYMBOL(set_auxio);

2
arch/sparc/kernel/chmc.c
View File

@ -664,7 +664,7 @@ static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 va
case 0x0:
bp->interleave = 16;
break;
};
}
/* UK[10] is reserved, and UK[11] is not set for the SDRAM
* bank size definition.

8
arch/sparc/kernel/entry.S
View File

@ -229,7 +229,7 @@ real_irq_entry:
#ifdef CONFIG_SMP
.globl patchme_maybe_smp_msg
cmp %l7, 12
cmp %l7, 11
patchme_maybe_smp_msg:
bgu maybe_smp4m_msg
nop
@ -293,7 +293,7 @@ maybe_smp4m_msg:
WRITE_PAUSE
wr %l4, PSR_ET, %psr
WRITE_PAUSE
sll %o2, 28, %o2 ! shift for simpler checks below
sll %o3, 28, %o2 ! shift for simpler checks below
maybe_smp4m_msg_check_single:
andcc %o2, 0x1, %g0
beq,a maybe_smp4m_msg_check_mask
@ -1604,7 +1604,7 @@ restore_current:
retl
nop
#ifdef CONFIG_PCI
#ifdef CONFIG_PCIC_PCI
#include <asm/pcic.h>
.align 4
@ -1650,7 +1650,7 @@ pcic_nmi_trap_patch:
rd %psr, %l0
.word 0
#endif /* CONFIG_PCI */
#endif /* CONFIG_PCIC_PCI */
.globl flushw_all
flushw_all:

31
arch/sparc/kernel/leon_kernel.c
View File

@ -236,6 +236,21 @@ static unsigned int _leon_build_device_irq(struct platform_device *op,
return leon_build_device_irq(real_irq, handle_simple_irq, "edge", 0);
}
void leon_update_virq_handling(unsigned int virq,
irq_flow_handler_t flow_handler,
const char *name, int do_ack)
{
unsigned long mask = (unsigned long)irq_get_chip_data(virq);
mask &= ~LEON_DO_ACK_HW;
if (do_ack)
mask |= LEON_DO_ACK_HW;
irq_set_chip_and_handler_name(virq, &leon_irq,
flow_handler, name);
irq_set_chip_data(virq, (void *)mask);
}
void __init leon_init_timers(irq_handler_t counter_fn)
{
int irq, eirq;
@ -361,6 +376,22 @@ void __init leon_init_timers(irq_handler_t counter_fn)
prom_halt();
}
#ifdef CONFIG_SMP
{
unsigned long flags;
/*
* In SMP, sun4m adds a IPI handler to IRQ trap handler that
* LEON never must take, sun4d and LEON overwrites the branch
* with a NOP.
*/
local_irq_save(flags);
patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
local_flush_cache_all();
local_irq_restore(flags);
}
#endif
LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl,
LEON3_GPTIMER_EN |
LEON3_GPTIMER_RL |

253
arch/sparc/kernel/leon_pci.c Normal file
View File

@ -0,0 +1,253 @@
/*
* leon_pci.c: LEON Host PCI support
*
* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
*
* Code is partially derived from pcic.c
*/
#include <linux/of_device.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <asm/leon.h>
#include <asm/leon_pci.h>
/* The LEON architecture does not rely on a BIOS or bootloader to setup
* PCI for us. The Linux generic routines are used to setup resources,
* reset values of confuration-space registers settings ae preseved.
*/
void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
{
struct pci_bus *root_bus;
root_bus = pci_scan_bus_parented(&ofdev->dev, 0, info->ops, info);
if (root_bus) {
root_bus->resource[0] = &info->io_space;
root_bus->resource[1] = &info->mem_space;
root_bus->resource[2] = NULL;
/* Init all PCI devices into PCI tree */
pci_bus_add_devices(root_bus);
/* Setup IRQs of all devices using custom routines */
pci_fixup_irqs(pci_common_swizzle, info->map_irq);
/* Assign devices with resources */
pci_assign_unassigned_resources();
}
}
/* PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
* accessed through a Window which is translated to low 64KB in PCI space, the
* first 4KB is not used so 60KB is available.
*
* This function is used by generic code to translate resource addresses into
* PCI addresses.
*/
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
struct leon_pci_info *info = dev->bus->sysdata;
region->start = res->start;
region->end = res->end;
if (res->flags & IORESOURCE_IO) {
region->start -= (info->io_space.start - 0x1000);
region->end -= (info->io_space.start - 0x1000);
}
}
EXPORT_SYMBOL(pcibios_resource_to_bus);
/* see pcibios_resource_to_bus() comment */
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region)
{
struct leon_pci_info *info = dev->bus->sysdata;
res->start = region->start;
res->end = region->end;
if (res->flags & IORESOURCE_IO) {
res->start += (info->io_space.start - 0x1000);
res->end += (info->io_space.start - 0x1000);
}
}
EXPORT_SYMBOL(pcibios_bus_to_resource);
void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
{
struct leon_pci_info *info = pbus->sysdata;
struct pci_dev *dev;
int i, has_io, has_mem;
u16 cmd;
/* Generic PCI bus probing sets these to point at
* &io{port,mem}_resouce which is wrong for us.
*/
if (pbus->self == NULL) {
pbus->resource[0] = &info->io_space;
pbus->resource[1] = &info->mem_space;
pbus->resource[2] = NULL;
}
list_for_each_entry(dev, &pbus->devices, bus_list) {
/*
* We can not rely on that the bootloader has enabled I/O
* or memory access to PCI devices. Instead we enable it here
* if the device has BARs of respective type.
*/
has_io = has_mem = 0;
for (i = 0; i < PCI_ROM_RESOURCE; i++) {
unsigned long f = dev->resource[i].flags;
if (f & IORESOURCE_IO)
has_io = 1;
else if (f & IORESOURCE_MEM)
has_mem = 1;
}
/* ROM BARs are mapped into 32-bit memory space */
if (dev->resource[PCI_ROM_RESOURCE].end != 0) {
dev->resource[PCI_ROM_RESOURCE].flags |=
IORESOURCE_ROM_ENABLE;
has_mem = 1;
}
pci_bus_read_config_word(pbus, dev->devfn, PCI_COMMAND, &cmd);
if (has_io && !(cmd & PCI_COMMAND_IO)) {
#ifdef CONFIG_PCI_DEBUG
printk(KERN_INFO "LEONPCI: Enabling I/O for dev %s\n",
pci_name(dev));
#endif
cmd |= PCI_COMMAND_IO;
pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
cmd);
}
if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
#ifdef CONFIG_PCI_DEBUG
printk(KERN_INFO "LEONPCI: Enabling MEMORY for dev"
"%s\n", pci_name(dev));
#endif
cmd |= PCI_COMMAND_MEMORY;
pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
cmd);
}
}
}
/*
* Other archs parse arguments here.
*/
char * __devinit pcibios_setup(char *str)
{
return str;
}
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
{
return res->start;
}
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
return pci_enable_resources(dev, mask);
}
struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
{
/*
* Currently the OpenBoot nodes are not connected with the PCI device,
* this is because the LEON PROM does not create PCI nodes. Eventually
* this will change and the same approach as pcic.c can be used to
* match PROM nodes with pci devices.
*/
return NULL;
}
EXPORT_SYMBOL(pci_device_to_OF_node);
void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
{
#ifdef CONFIG_PCI_DEBUG
printk(KERN_DEBUG "LEONPCI: Assigning IRQ %02d to %s\n", irq,
pci_name(dev));
#endif
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
/* in/out routines taken from pcic.c
*
* This probably belongs here rather than ioport.c because
* we do not want this crud linked into SBus kernels.
* Also, think for a moment about likes of floppy.c that
* include architecture specific parts. They may want to redefine ins/outs.
*
* We do not use horrible macros here because we want to
* advance pointer by sizeof(size).
*/
void outsb(unsigned long addr, const void *src, unsigned long count)
{
while (count) {
count -= 1;
outb(*(const char *)src, addr);
src += 1;
/* addr += 1; */
}
}
EXPORT_SYMBOL(outsb);
void outsw(unsigned long addr, const void *src, unsigned long count)
{
while (count) {
count -= 2;
outw(*(const short *)src, addr);
src += 2;
/* addr += 2; */
}
}
EXPORT_SYMBOL(outsw);
void outsl(unsigned long addr, const void *src, unsigned long count)
{
while (count) {
count -= 4;
outl(*(const long *)src, addr);
src += 4;
/* addr += 4; */
}
}
EXPORT_SYMBOL(outsl);
void insb(unsigned long addr, void *dst, unsigned long count)
{
while (count) {
count -= 1;
*(unsigned char *)dst = inb(addr);
dst += 1;
/* addr += 1; */
}
}
EXPORT_SYMBOL(insb);
void insw(unsigned long addr, void *dst, unsigned long count)
{
while (count) {
count -= 2;
*(unsigned short *)dst = inw(addr);
dst += 2;
/* addr += 2; */
}
}
EXPORT_SYMBOL(insw);
void insl(unsigned long addr, void *dst, unsigned long count)
{
while (count) {
count -= 4;
/*
* XXX I am sure we are in for an unaligned trap here.
*/
*(unsigned long *)dst = inl(addr);
dst += 4;
/* addr += 4; */
}
}
EXPORT_SYMBOL(insl);

897
arch/sparc/kernel/leon_pci_grpci2.c Normal file
View File

@ -0,0 +1,897 @@
/*
* leon_pci_grpci2.c: GRPCI2 Host PCI driver
*
* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
*
*/
#include <linux/of_device.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/leon.h>
#include <asm/vaddrs.h>
#include <asm/sections.h>
#include <asm/leon_pci.h>
#include "irq.h"
struct grpci2_barcfg {
unsigned long pciadr; /* PCI Space Address */
unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
};
/* Device Node Configuration options:
* - barcfgs : Custom Configuration of Host's 6 target BARs
* - irq_mask : Limit which PCI interrupts are enabled
* - do_reset : Force PCI Reset on startup
*
* barcfgs
* =======
*
* Optional custom Target BAR configuration (see struct grpci2_barcfg). All
* addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
*
* -1 means not configured (let host driver do default setup).
*
* [i*2+0] = PCI Address of BAR[i] on target interface
* [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
*
*
* irq_mask
* ========
*
* Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
* all are enabled. Use this when PCI interrupt pins are floating on PCB.
* int, len=4.
* bit0 = PCI INTA#
* bit1 = PCI INTB#
* bit2 = PCI INTC#
* bit3 = PCI INTD#
*
*
* reset
* =====
*
* Force PCI reset on startup. int, len=4
*/
/* Enable Debugging Configuration Space Access */
#undef GRPCI2_DEBUG_CFGACCESS
/*
* GRPCI2 APB Register MAP
*/
struct grpci2_regs {
unsigned int ctrl; /* 0x00 Control */
unsigned int sts_cap; /* 0x04 Status / Capabilities */
int res1; /* 0x08 */
unsigned int io_map; /* 0x0C I/O Map address */
unsigned int dma_ctrl; /* 0x10 DMA */
unsigned int dma_bdbase; /* 0x14 DMA */
int res2[2]; /* 0x18 */
unsigned int bars[6]; /* 0x20 read-only PCI BARs */
int res3[2]; /* 0x38 */
unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
/* PCI Trace Buffer Registers (OPTIONAL) */
unsigned int t_ctrl; /* 0x80 */
unsigned int t_cnt; /* 0x84 */
unsigned int t_adpat; /* 0x88 */
unsigned int t_admask; /* 0x8C */
unsigned int t_sigpat; /* 0x90 */
unsigned int t_sigmask; /* 0x94 */
unsigned int t_adstate; /* 0x98 */
unsigned int t_sigstate; /* 0x9C */
};
#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
#define CTRL_BUS_BIT 16
#define CTRL_RESET (1<<31)
#define CTRL_SI (1<<27)
#define CTRL_PE (1<<26)
#define CTRL_EI (1<<25)
#define CTRL_ER (1<<24)
#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
#define CTRL_HOSTINT 0xf
#define STS_HOST_BIT 31
#define STS_MST_BIT 30
#define STS_TAR_BIT 29
#define STS_DMA_BIT 28
#define STS_DI_BIT 27
#define STS_HI_BIT 26
#define STS_IRQMODE_BIT 24
#define STS_TRACE_BIT 23
#define STS_CFGERRVALID_BIT 20
#define STS_CFGERR_BIT 19
#define STS_INTTYPE_BIT 12
#define STS_INTSTS_BIT 8
#define STS_FDEPTH_BIT 2
#define STS_FNUM_BIT 0
#define STS_HOST (1<<STS_HOST_BIT)
#define STS_MST (1<<STS_MST_BIT)
#define STS_TAR (1<<STS_TAR_BIT)
#define STS_DMA (1<<STS_DMA_BIT)
#define STS_DI (1<<STS_DI_BIT)
#define STS_HI (1<<STS_HI_BIT)
#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
#define STS_TRACE (1<<STS_TRACE_BIT)
#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
#define STS_CFGERR (1<<STS_CFGERR_BIT)
#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
#define STS_FNUM (0x3<<STS_FNUM_BIT)
#define STS_ISYSERR (1<<17)
#define STS_IDMA (1<<16)
#define STS_IDMAERR (1<<15)
#define STS_IMSTABRT (1<<14)
#define STS_ITGTABRT (1<<13)
#define STS_IPARERR (1<<12)
#define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
struct grpci2_bd_chan {
unsigned int ctrl; /* 0x00 DMA Control */
unsigned int nchan; /* 0x04 Next DMA Channel Address */
unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
unsigned int res; /* 0x0C Reserved */
};
#define BD_CHAN_EN 0x80000000
#define BD_CHAN_TYPE 0x00300000
#define BD_CHAN_BDCNT 0x0000ffff
#define BD_CHAN_EN_BIT 31
#define BD_CHAN_TYPE_BIT 20
#define BD_CHAN_BDCNT_BIT 0
struct grpci2_bd_data {
unsigned int ctrl; /* 0x00 DMA Data Control */
unsigned int pci_adr; /* 0x04 PCI Start Address */
unsigned int ahb_adr; /* 0x08 AHB Start address */
unsigned int next; /* 0x0C Next Data Descriptor in chan */
};
#define BD_DATA_EN 0x80000000
#define BD_DATA_IE 0x40000000
#define BD_DATA_DR 0x20000000
#define BD_DATA_TYPE 0x00300000
#define BD_DATA_ER 0x00080000
#define BD_DATA_LEN 0x0000ffff
#define BD_DATA_EN_BIT 31
#define BD_DATA_IE_BIT 30
#define BD_DATA_DR_BIT 29
#define BD_DATA_TYPE_BIT 20
#define BD_DATA_ER_BIT 19
#define BD_DATA_LEN_BIT 0
/* GRPCI2 Capability */
struct grpci2_cap_first {
unsigned int ctrl;
unsigned int pci2ahb_map[6];
unsigned int ext2ahb_map;
unsigned int io_map;
unsigned int pcibar_size[6];
};
#define CAP9_CTRL_OFS 0
#define CAP9_BAR_OFS 0x4
#define CAP9_IOMAP_OFS 0x20
#define CAP9_BARSIZE_OFS 0x24
struct grpci2_priv {
struct leon_pci_info info; /* must be on top of this structure */
struct grpci2_regs *regs;
char irq;
char irq_mode; /* IRQ Mode from CAPSTS REG */
char bt_enabled;
char do_reset;
char irq_mask;
u32 pciid; /* PCI ID of Host */
unsigned char irq_map[4];
/* Virtual IRQ numbers */
unsigned int virq_err;
unsigned int virq_dma;
/* AHB PCI Windows */
unsigned long pci_area; /* MEMORY */
unsigned long pci_area_end;
unsigned long pci_io; /* I/O */
unsigned long pci_conf; /* CONFIGURATION */
unsigned long pci_conf_end;
unsigned long pci_io_va;
struct grpci2_barcfg tgtbars[6];
};
DEFINE_SPINLOCK(grpci2_dev_lock);
struct grpci2_priv *grpci2priv;
int grpci2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
struct grpci2_priv *priv = dev->bus->sysdata;
int irq_group;
/* Use default IRQ decoding on PCI BUS0 according slot numbering */
irq_group = slot & 0x3;
pin = ((pin - 1) + irq_group) & 0x3;
return priv->irq_map[pin];
}
static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
unsigned int devfn, int where, u32 *val)
{
unsigned int *pci_conf;
unsigned long flags;
u32 tmp;
if (where & 0x3)
return -EINVAL;
if (bus == 0 && PCI_SLOT(devfn) != 0)
devfn += (0x8 * 6);
/* Select bus */
spin_lock_irqsave(&grpci2_dev_lock, flags);
REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
(bus << 16));
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
/* clear old status */
REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
pci_conf = (unsigned int *) (priv->pci_conf |
(devfn << 8) | (where & 0xfc));
tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
/* Wait until GRPCI2 signals that CFG access is done, it should be
* done instantaneously unless a DMA operation is ongoing...
*/
while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
;
if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
*val = 0xffffffff;
} else {
/* Bus always little endian (unaffected by byte-swapping) */
*val = flip_dword(tmp);
}
return 0;
}
static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
unsigned int devfn, int where, u32 *val)
{
u32 v;
int ret;
if (where & 0x1)
return -EINVAL;
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
*val = 0xffff & (v >> (8 * (where & 0x3)));
return ret;
}
static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
unsigned int devfn, int where, u32 *val)
{
u32 v;
int ret;
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
*val = 0xff & (v >> (8 * (where & 3)));
return ret;
}
static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
unsigned int devfn, int where, u32 val)
{
unsigned int *pci_conf;
unsigned long flags;
if (where & 0x3)
return -EINVAL;
if (bus == 0 && PCI_SLOT(devfn) != 0)
devfn += (0x8 * 6);
/* Select bus */
spin_lock_irqsave(&grpci2_dev_lock, flags);
REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
(bus << 16));
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
/* clear old status */
REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
pci_conf = (unsigned int *) (priv->pci_conf |
(devfn << 8) | (where & 0xfc));
LEON3_BYPASS_STORE_PA(pci_conf, flip_dword(val));
/* Wait until GRPCI2 signals that CFG access is done, it should be
* done instantaneously unless a DMA operation is ongoing...
*/
while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
;
return 0;
}
static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
unsigned int devfn, int where, u32 val)
{
int ret;
u32 v;
if (where & 0x1)
return -EINVAL;
ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
if (ret)
return ret;
v = (v & ~(0xffff << (8 * (where & 0x3)))) |
((0xffff & val) << (8 * (where & 0x3)));
return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
}
static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
unsigned int devfn, int where, u32 val)
{
int ret;
u32 v;
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
if (ret != 0)
return ret;
v = (v & ~(0xff << (8 * (where & 0x3)))) |
((0xff & val) << (8 * (where & 0x3)));
return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
}
/* Read from Configuration Space. When entering here the PCI layer has taken
* the pci_lock spinlock and IRQ is off.
*/
static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct grpci2_priv *priv = grpci2priv;
unsigned int busno = bus->number;
int ret;
if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) {
*val = ~0;
return 0;
}
switch (size) {
case 1:
ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
break;
case 2:
ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
break;
case 4:
ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
break;
default:
ret = -EINVAL;
break;
}
#ifdef GRPCI2_DEBUG_CFGACCESS
printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
"size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
*val, size);
#endif
return ret;
}
/* Write to Configuration Space. When entering here the PCI layer has taken
* the pci_lock spinlock and IRQ is off.
*/
static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
struct grpci2_priv *priv = grpci2priv;
unsigned int busno = bus->number;
if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0))
return 0;
#ifdef GRPCI2_DEBUG_CFGACCESS
printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
"val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
where, size, val);
#endif
switch (size) {
default:
return -EINVAL;
case 1:
return grpci2_cfg_w8(priv, busno, devfn, where, val);
case 2:
return grpci2_cfg_w16(priv, busno, devfn, where, val);
case 4:
return grpci2_cfg_w32(priv, busno, devfn, where, val);
}
}
static struct pci_ops grpci2_ops = {
.read = grpci2_read_config,
.write = grpci2_write_config,
};
/* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
* 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
* this is not needed and the standard IRQ controller can be used.
*/
static void grpci2_mask_irq(struct irq_data *data)
{
unsigned long flags;
unsigned int irqidx;
struct grpci2_priv *priv = grpci2priv;
irqidx = (unsigned int)data->chip_data - 1;
if (irqidx > 3) /* only mask PCI interrupts here */
return;
spin_lock_irqsave(&grpci2_dev_lock, flags);
REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
}
static void grpci2_unmask_irq(struct irq_data *data)
{
unsigned long flags;
unsigned int irqidx;
struct grpci2_priv *priv = grpci2priv;
irqidx = (unsigned int)data->chip_data - 1;
if (irqidx > 3) /* only unmask PCI interrupts here */
return;
spin_lock_irqsave(&grpci2_dev_lock, flags);
REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
spin_unlock_irqrestore(&grpci2_dev_lock, flags);
}
static unsigned int grpci2_startup_irq(struct irq_data *data)
{
grpci2_unmask_irq(data);
return 0;
}
static void grpci2_shutdown_irq(struct irq_data *data)
{
grpci2_mask_irq(data);
}
static struct irq_chip grpci2_irq = {
.name = "grpci2",
.irq_startup = grpci2_startup_irq,
.irq_shutdown = grpci2_shutdown_irq,
.irq_mask = grpci2_mask_irq,
.irq_unmask = grpci2_unmask_irq,
};
/* Handle one or multiple IRQs from the PCI core */
static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
{
struct grpci2_priv *priv = grpci2priv;
int i, ack = 0;
unsigned int ctrl, sts_cap, pci_ints;
ctrl = REGLOAD(priv->regs->ctrl);
sts_cap = REGLOAD(priv->regs->sts_cap);
/* Error Interrupt? */
if (sts_cap & STS_ERR_IRQ) {
generic_handle_irq(priv->virq_err);
ack = 1;
}
/* PCI Interrupt? */
pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
if (pci_ints) {
/* Call respective PCI Interrupt handler */
for (i = 0; i < 4; i++) {
if (pci_ints & (1 << i))
generic_handle_irq(priv->irq_map[i]);
}
ack = 1;
}
/*
* Decode DMA Interrupt only when shared with Err and PCI INTX#, when
* the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
* goes directly to DMA ISR.
*/
if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
generic_handle_irq(priv->virq_dma);
ack = 1;
}
/*
* Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
* Controller, this must be done after IRQ sources have been handled to
* avoid double IRQ generation
*/
if (ack)
desc->irq_data.chip->irq_eoi(&desc->irq_data);
}
/* Create a virtual IRQ */
static unsigned int grpci2_build_device_irq(unsigned int irq)
{
unsigned int virq = 0, pil;
pil = 1 << 8;
virq = irq_alloc(irq, pil);
if (virq == 0)
goto out;
irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
"pcilvl");
irq_set_chip_data(virq, (void *)irq);
out:
return virq;
}
void grpci2_hw_init(struct grpci2_priv *priv)
{
u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
struct grpci2_regs *regs = priv->regs;
int i;
struct grpci2_barcfg *barcfg = priv->tgtbars;
/* Reset any earlier setup */
if (priv->do_reset) {
printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
REGSTORE(regs->ctrl, CTRL_RESET);
ssleep(1); /* Wait for boards to settle */
}
REGSTORE(regs->ctrl, 0);
REGSTORE(regs->sts_cap, ~0); /* Clear Status */
REGSTORE(regs->dma_ctrl, 0);
REGSTORE(regs->dma_bdbase, 0);
/* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
* Each AHB master has it's own mapping registers. Max 16 AHB masters.
*/
for (i = 0; i < 16; i++)
REGSTORE(regs->ahbmst_map[i], priv->pci_area);
/* Get the GRPCI2 Host PCI ID */
grpci2_cfg_r32(priv, 0, 0, PCI_VENDOR_ID, &priv->pciid);
/* Get address to first (always defined) capability structure */
grpci2_cfg_r8(priv, 0, 0, PCI_CAPABILITY_LIST, &capptr);
/* Enable/Disable Byte twisting */
grpci2_cfg_r32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, &io_map);
io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, io_map);
/* Setup the Host's PCI Target BARs for other peripherals to access,
* and do DMA to the host's memory. The target BARs can be sized and
* enabled individually.
*
* User may set custom target BARs, but default is:
* The first BARs is used to map kernel low (DMA is part of normal
* region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
* PCI bus, the other BARs are disabled. We assume that the first BAR
* is always available.
*/
for (i = 0; i < 6; i++) {
if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
/* Target BARs must have the proper alignment */
ahbadr = barcfg[i].ahbadr;
pciadr = barcfg[i].pciadr;
bar_sz = ((pciadr - 1) & ~pciadr) + 1;
} else {
if (i == 0) {
/* Map main memory */
bar_sz = 0xf0000008; /* 256MB prefetchable */
ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
(unsigned long) &_end));
pciadr = ahbadr;
} else {
bar_sz = 0;
ahbadr = 0;
pciadr = 0;
}
}
grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BARSIZE_OFS+i*4, bar_sz);
grpci2_cfg_w32(priv, 0, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
i, pciadr, ahbadr);
}
/* set as bus master and enable pci memory responses */
grpci2_cfg_r32(priv, 0, 0, PCI_COMMAND, &data);
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
grpci2_cfg_w32(priv, 0, 0, PCI_COMMAND, data);
/* Enable Error respone (CPU-TRAP) on illegal memory access. */
REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
}
static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
{
printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
return IRQ_NONE;
}
/* Handle GRPCI2 Error Interrupt */
static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
{
struct grpci2_priv *priv = arg;
struct grpci2_regs *regs = priv->regs;
unsigned int status;
status = REGLOAD(regs->sts_cap);
if ((status & STS_ERR_IRQ) == 0)
return IRQ_NONE;
if (status & STS_IPARERR)
printk(KERN_ERR "GRPCI2: Parity Error\n");
if (status & STS_ITGTABRT)
printk(KERN_ERR "GRPCI2: Target Abort\n");
if (status & STS_IMSTABRT)
printk(KERN_ERR "GRPCI2: Master Abort\n");
if (status & STS_ISYSERR)
printk(KERN_ERR "GRPCI2: System Error\n");
/* Clear handled INT TYPE IRQs */
REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
return IRQ_HANDLED;
}
static int __devinit grpci2_of_probe(struct platform_device *ofdev)
{
struct grpci2_regs *regs;
struct grpci2_priv *priv;
int err, i, len;
const int *tmp;
unsigned int capability;
if (grpci2priv) {
printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
return -ENODEV;
}
if (ofdev->num_resources < 3) {
printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
return -EIO;
}
/* Find Device Address */
regs = of_ioremap(&ofdev->resource[0], 0,
resource_size(&ofdev->resource[0]),
"grlib-grpci2 regs");
if (regs == NULL) {
printk(KERN_ERR "GRPCI2: ioremap failed\n");
return -EIO;
}
/*
* Check that we're in Host Slot and that we can act as a Host Bridge
* and not only as target.
*/
capability = REGLOAD(regs->sts_cap);
if ((capability & STS_HOST) || !(capability & STS_MST)) {
printk(KERN_INFO "GRPCI2: not in host system slot\n");
err = -EIO;
goto err1;
}
priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
if (grpci2priv == NULL) {
err = -ENOMEM;
goto err1;
}
memset(grpci2priv, 0, sizeof(*grpci2priv));
priv->regs = regs;
priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
/* Byte twisting should be made configurable from kernel command line */
priv->bt_enabled = 1;
/* Let user do custom Target BAR assignment */
tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
if (tmp && (len == 2*4*6))
memcpy(priv->tgtbars, tmp, 2*4*6);
else
memset(priv->tgtbars, -1, 2*4*6);
/* Limit IRQ unmasking in irq_mode 2 and 3 */
tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
if (tmp && (len == 4))
priv->do_reset = *tmp;
else
priv->irq_mask = 0xf;
/* Optional PCI reset. Force PCI reset on startup */
tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
if (tmp && (len == 4))
priv->do_reset = *tmp;
else
priv->do_reset = 0;
/* Find PCI Memory, I/O and Configuration Space Windows */
priv->pci_area = ofdev->resource[1].start;
priv->pci_area_end = ofdev->resource[1].end+1;
priv->pci_io = ofdev->resource[2].start;
priv->pci_conf = ofdev->resource[2].start + 0x10000;
priv->pci_conf_end = priv->pci_conf + 0x10000;
priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
if (!priv->pci_io_va) {
err = -EIO;
goto err2;
}
printk(KERN_INFO
"GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
" I/O SPACE [0x%08lx - 0x%08lx]\n"
" CONFIG SPACE [0x%08lx - 0x%08lx]\n",
priv->pci_area, priv->pci_area_end-1,
priv->pci_io, priv->pci_conf-1,
priv->pci_conf, priv->pci_conf_end-1);
/*
* I/O Space resources in I/O Window mapped into Virtual Adr Space
* We never use low 4KB because some devices seem have problems using
* address 0.
*/
memset(&priv->info.io_space, 0, sizeof(struct resource));
priv->info.io_space.name = "GRPCI2 PCI I/O Space";
priv->info.io_space.start = priv->pci_io_va + 0x1000;
priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
priv->info.io_space.flags = IORESOURCE_IO;
/*
* GRPCI2 has no prefetchable memory, map everything as
* non-prefetchable memory
*/
memset(&priv->info.mem_space, 0, sizeof(struct resource));
priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
priv->info.mem_space.start = priv->pci_area;
priv->info.mem_space.end = priv->pci_area_end - 1;
priv->info.mem_space.flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
goto err3;
if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
goto err4;
grpci2_hw_init(priv);
/*
* Get PCI Interrupt to System IRQ mapping and setup IRQ handling
* Error IRQ always on PCI INTA.
*/
if (priv->irq_mode < 2) {
/* All PCI interrupts are shared using the same system IRQ */
leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
"pcilvl", 0);
priv->irq_map[0] = grpci2_build_device_irq(1);
priv->irq_map[1] = grpci2_build_device_irq(2);
priv->irq_map[2] = grpci2_build_device_irq(3);
priv->irq_map[3] = grpci2_build_device_irq(4);
priv->virq_err = grpci2_build_device_irq(5);
if (priv->irq_mode & 1)
priv->virq_dma = ofdev->archdata.irqs[1];
else
priv->virq_dma = grpci2_build_device_irq(6);
/* Enable IRQs on LEON IRQ controller */
err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
"GRPCI2_JUMP", priv);
if (err)
printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
} else {
/* All PCI interrupts have an unique IRQ interrupt */
for (i = 0; i < 4; i++) {
/* Make LEON IRQ layer handle level IRQ by acking */
leon_update_virq_handling(ofdev->archdata.irqs[i],
handle_fasteoi_irq, "pcilvl",
1);
priv->irq_map[i] = ofdev->archdata.irqs[i];
}
priv->virq_err = priv->irq_map[0];
if (priv->irq_mode & 1)
priv->virq_dma = ofdev->archdata.irqs[4];
else
priv->virq_dma = priv->irq_map[0];
/* Unmask all PCI interrupts, request_irq will not do that */
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
}
/* Setup IRQ handler for non-configuration space access errors */
err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
"GRPCI2_ERR", priv);
if (err) {
printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
goto err5;
}
/*
* Enable Error Interrupts. PCI interrupts are unmasked once request_irq
* is called by the PCI Device drivers
*/
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
/* Init common layer and scan buses */
priv->info.ops = &grpci2_ops;
priv->info.map_irq = grpci2_map_irq;
leon_pci_init(ofdev, &priv->info);
return 0;
err5:
release_resource(&priv->info.io_space);
err4:
release_resource(&priv->info.mem_space);
err3:
err = -ENOMEM;
iounmap((void *)priv->pci_io_va);
err2:
kfree(priv);
err1:
of_iounmap(&ofdev->resource[0], regs,
resource_size(&ofdev->resource[0]));
return err;
}
static struct of_device_id grpci2_of_match[] = {
{
.name = "GAISLER_GRPCI2",
},
{
.name = "01_07c",
},
{},
};
static struct platform_driver grpci2_of_driver = {
.driver = {
.name = "grpci2",
.owner = THIS_MODULE,
.of_match_table = grpci2_of_match,
},
.probe = grpci2_of_probe,
};
static int __init grpci2_init(void)
{
return platform_driver_register(&grpci2_of_driver);
}
subsys_initcall(grpci2_init);

2
arch/sparc/kernel/module.c
View File

@ -214,7 +214,7 @@ int apply_relocate_add(Elf_Shdr *sechdrs,
me->name,
(int) (ELF_R_TYPE(rel[i].r_info) & 0xff));
return -ENOEXEC;
};
}
}
return 0;
}

4
arch/sparc/kernel/pci_common.c
View File

@ -281,7 +281,7 @@ static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
case 4:
*value = ret & 0xffffffff;
break;
};
}
return PCIBIOS_SUCCESSFUL;
@ -456,7 +456,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
default:
break;
};
}
}
if (!saw_io || !saw_mem) {

6
arch/sparc/kernel/pci_schizo.c
View File

@ -264,7 +264,7 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
default:
type_string = "ECC Error";
break;
};
}
printk("%s: IOMMU Error, type[%s]\n",
pbm->name, type_string);
@ -319,7 +319,7 @@ static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
default:
type_string = "ECC Error";
break;
};
}
printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
"sz(%dK) vpg(%08lx)]\n",
pbm->name, i, type_string,
@ -1328,7 +1328,7 @@ static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm,
default:
chipset_name = "SCHIZO";
break;
};
}
/* For SCHIZO, three OBP regs:
* 1) PBM controller regs

2
arch/sparc/kernel/prom_irqtrans.c
View File

@ -694,7 +694,7 @@ static unsigned int sbus_of_build_irq(struct device_node *dp,
case 3:
iclr = reg_base + SYSIO_ICLR_SLOT3;
break;
};
}
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
}

2
arch/sparc/kernel/psycho_common.c
View File

@ -228,7 +228,7 @@ void psycho_check_iommu_error(struct pci_pbm_info *pbm,
default:
type_str = "ECC Error";
break;
};
}
printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
pbm->name, type_str);

4
arch/sparc/kernel/sbus.c
View File

@ -97,7 +97,7 @@ void sbus_set_sbus64(struct device *dev, int bursts)
default:
return;
};
}
val = upa_readq(cfg_reg);
if (val & (1UL << 14UL)) {
@ -244,7 +244,7 @@ static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
case 3:
iclr = reg_base + SYSIO_ICLR_SLOT3;
break;
};
}
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
}

2
arch/sparc/kernel/setup_32.c
View File

@ -267,7 +267,7 @@ void __init setup_arch(char **cmdline_p)
default:
printk("UNKNOWN!\n");
break;
};
}
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;

2
arch/sparc/kernel/setup_64.c
View File

@ -209,7 +209,7 @@ void __init per_cpu_patch(void)
default:
prom_printf("Unknown cpu type, halting.\n");
prom_halt();
};
}
*(unsigned int *) (addr + 0) = insns[0];
wmb();

6
arch/sparc/kernel/smp_32.c
View File

@ -114,7 +114,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
printk("UNKNOWN!\n");
BUG();
break;
};
}
}
void cpu_panic(void)
@ -374,7 +374,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
printk("UNKNOWN!\n");
BUG();
break;
};
}
}
/* Set this up early so that things like the scheduler can init
@ -447,7 +447,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
printk("UNKNOWN!\n");
BUG();
break;
};
}
if (!ret) {
cpumask_set_cpu(cpu, &smp_commenced_mask);

152
arch/sparc/kernel/sun4d_irq.c
View File

@ -103,10 +103,9 @@ static void sun4d_sbus_handler_irq(int sbusl)
sbil = (sbusl << 2);
/* Loop for each pending SBI */
for (sbino = 0; bus_mask; sbino++) {
for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
unsigned int idx, mask;
bus_mask >>= 1;
if (!(bus_mask & 1))
continue;
/* XXX This seems to ACK the irq twice. acquire_sbi()
@ -118,19 +117,16 @@ static void sun4d_sbus_handler_irq(int sbusl)
mask &= (0xf << sbil);
/* Loop for each pending SBI slot */
idx = 0;
slot = (1 << sbil);
while (mask != 0) {
for (idx = 0; mask != 0; idx++, slot <<= 1) {
unsigned int pil;
struct irq_bucket *p;
idx++;
slot <<= 1;
if (!(mask & slot))
continue;
mask &= ~slot;
pil = sun4d_encode_irq(sbino, sbil, idx);
pil = sun4d_encode_irq(sbino, sbusl, idx);
p = irq_map[pil];
while (p) {
@ -218,10 +214,10 @@ static void sun4d_unmask_irq(struct irq_data *data)
#ifdef CONFIG_SMP
spin_lock_irqsave(&sun4d_imsk_lock, flags);
cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | ~(1 << real_irq));
cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
#else
cc_set_imsk(cc_get_imsk() | ~(1 << real_irq));
cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
#endif
}
@ -299,58 +295,19 @@ static void __init sun4d_load_profile_irqs(void)
}
}
unsigned int sun4d_build_device_irq(struct platform_device *op,
unsigned int real_irq)
unsigned int _sun4d_build_device_irq(unsigned int real_irq,
unsigned int pil,
unsigned int board)
{
struct device_node *dp = op->dev.of_node;
struct device_node *io_unit, *sbi = dp->parent;
const struct linux_prom_registers *regs;
struct sun4d_handler_data *handler_data;
unsigned int pil;
unsigned int irq;
int board, slot;
int sbusl;
irq = 0;
while (sbi) {
if (!strcmp(sbi->name, "sbi"))
break;
sbi = sbi->parent;
}
if (!sbi)
goto err_out;
regs = of_get_property(dp, "reg", NULL);
if (!regs)
goto err_out;
slot = regs->which_io;
/*
* If SBI's parent is not io-unit or the io-unit lacks
* a "board#" property, something is very wrong.
*/
if (!sbi->parent || strcmp(sbi->parent->name, "io-unit")) {
printk("%s: Error, parent is not io-unit.\n", sbi->full_name);
goto err_out;
}
io_unit = sbi->parent;
board = of_getintprop_default(io_unit, "board#", -1);
if (board == -1) {
printk("%s: Error, lacks board# property.\n", io_unit->full_name);
goto err_out;
}
sbusl = pil_to_sbus[real_irq];
if (sbusl)
pil = sun4d_encode_irq(board, sbusl, slot);
else
pil = real_irq;
irq = irq_alloc(real_irq, pil);
if (irq == 0)
if (irq == 0) {
prom_printf("IRQ: allocate for %d %d %d failed\n",
real_irq, pil, board);
goto err_out;
}
handler_data = irq_get_handler_data(irq);
if (unlikely(handler_data))
@ -368,9 +325,80 @@ unsigned int sun4d_build_device_irq(struct platform_device *op,
irq_set_handler_data(irq, handler_data);
err_out:
return real_irq;
return irq;
}
unsigned int sun4d_build_device_irq(struct platform_device *op,
unsigned int real_irq)
{
struct device_node *dp = op->dev.of_node;
struct device_node *board_parent, *bus = dp->parent;
char *bus_connection;
const struct linux_prom_registers *regs;
unsigned int pil;
unsigned int irq;
int board, slot;
int sbusl;
irq = real_irq;
while (bus) {
if (!strcmp(bus->name, "sbi")) {
bus_connection = "io-unit";
break;
}
if (!strcmp(bus->name, "bootbus")) {
bus_connection = "cpu-unit";
break;
}
bus = bus->parent;
}
if (!bus)
goto err_out;
regs = of_get_property(dp, "reg", NULL);
if (!regs)
goto err_out;
slot = regs->which_io;
/*
* If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
* lacks a "board#" property, something is very wrong.
*/
if (!bus->parent || strcmp(bus->parent->name, bus_connection)) {
printk(KERN_ERR "%s: Error, parent is not %s.\n",
bus->full_name, bus_connection);
goto err_out;
}
board_parent = bus->parent;
board = of_getintprop_default(board_parent, "board#", -1);
if (board == -1) {
printk(KERN_ERR "%s: Error, lacks board# property.\n",
board_parent->full_name);
goto err_out;
}
sbusl = pil_to_sbus[real_irq];
if (sbusl)
pil = sun4d_encode_irq(board, sbusl, slot);
else
pil = real_irq;
irq = _sun4d_build_device_irq(real_irq, pil, board);
err_out:
return irq;
}
unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
{
return _sun4d_build_device_irq(real_irq, real_irq, board);
}
static void __init sun4d_fixup_trap_table(void)
{
#ifdef CONFIG_SMP
@ -402,6 +430,7 @@ static void __init sun4d_init_timers(irq_handler_t counter_fn)
unsigned int irq;
const u32 *reg;
int err;
int board;
dp = of_find_node_by_name(NULL, "cpu-unit");
if (!dp) {
@ -414,12 +443,19 @@ static void __init sun4d_init_timers(irq_handler_t counter_fn)
* bootbus.
*/
reg = of_get_property(dp, "reg", NULL);
of_node_put(dp);
if (!reg) {
prom_printf("sun4d_init_timers: No reg property\n");
prom_halt();
}
board = of_getintprop_default(dp, "board#", -1);
if (board == -1) {
prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
prom_halt();
}
of_node_put(dp);
res.start = reg[1];
res.end = reg[2] - 1;
res.flags = reg[0] & 0xff;
@ -434,7 +470,7 @@ static void __init sun4d_init_timers(irq_handler_t counter_fn)
master_l10_counter = &sun4d_timers->l10_cur_count;
irq = sun4d_build_device_irq(NULL, SUN4D_TIMER_IRQ);
irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
if (err) {
prom_printf("sun4d_init_timers: request_irq() failed with %d\n",

2
arch/sparc/kernel/sys_sparc32.c
View File

@ -109,7 +109,7 @@ asmlinkage long compat_sys_ipc(u32 call, u32 first, u32 second, u32 third, compa
default:
return -ENOSYS;
};
}
return -ENOSYS;
}

6
arch/sparc/kernel/sys_sparc_64.c
View File

@ -460,7 +460,7 @@ SYSCALL_DEFINE6(sparc_ipc, unsigned int, call, int, first, unsigned long, second
default:
err = -ENOSYS;
goto out;
};
}
}
if (call <= MSGCTL) {
switch (call) {
@ -481,7 +481,7 @@ SYSCALL_DEFINE6(sparc_ipc, unsigned int, call, int, first, unsigned long, second
default:
err = -ENOSYS;
goto out;
};
}
}
if (call <= SHMCTL) {
switch (call) {
@ -507,7 +507,7 @@ SYSCALL_DEFINE6(sparc_ipc, unsigned int, call, int, first, unsigned long, second
default:
err = -ENOSYS;
goto out;
};
}
} else {
err = -ENOSYS;
}

2
arch/sparc/kernel/time_64.c
View File

@ -708,7 +708,7 @@ static void sparc64_timer_setup(enum clock_event_mode mode,
case CLOCK_EVT_MODE_UNUSED:
WARN_ON(1);
break;
};
}
}
static struct clock_event_device sparc64_clockevent = {

2
arch/sparc/kernel/traps_64.c
View File

@ -1804,7 +1804,7 @@ static const char *sun4v_err_type_to_str(u32 type)
return "warning resumable";
default:
return "unknown";
};
}
}
static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)

6
arch/sparc/kernel/unaligned_64.c
View File

@ -211,7 +211,7 @@ static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
default:
BUG();
break;
};
}
}
return __do_int_store(dst_addr, size, src_val, asi);
}
@ -328,7 +328,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
case ASI_SNFL:
asi &= ~0x08;
break;
};
}
switch (dir) {
case load:
reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
@ -351,7 +351,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
default:
BUG();
break;
};
}
*reg_addr = val_in;
}
break;

6
arch/sparc/kernel/us2e_cpufreq.c
View File

@ -176,7 +176,7 @@ static unsigned long index_to_estar_mode(unsigned int index)
default:
BUG();
};
}
}
static unsigned long index_to_divisor(unsigned int index)
@ -199,7 +199,7 @@ static unsigned long index_to_divisor(unsigned int index)
default:
BUG();
};
}
}
static unsigned long estar_to_divisor(unsigned long estar)
@ -224,7 +224,7 @@ static unsigned long estar_to_divisor(unsigned long estar)
break;
default:
BUG();
};
}
return ret;
}

4
arch/sparc/kernel/us3_cpufreq.c
View File

@ -71,7 +71,7 @@ static unsigned long get_current_freq(unsigned int cpu, unsigned long safari_cfg
break;
default:
BUG();
};
}
return ret;
}
@ -125,7 +125,7 @@ static void us3_set_cpu_divider_index(unsigned int cpu, unsigned int index)
default:
BUG();
};
}
reg = read_safari_cfg();

2
arch/sparc/kernel/viohs.c
View File

@ -363,7 +363,7 @@ static int process_ver(struct vio_driver_state *vio, struct vio_ver_info *pkt)
default:
return handshake_failure(vio);
};
}
}
static int process_attr(struct vio_driver_state *vio, void *pkt)

14
arch/sparc/kernel/visemul.c
View File

@ -334,7 +334,7 @@ static void edge(struct pt_regs *regs, unsigned int insn, unsigned int opf)
left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
break;
};
}
if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
rd_val = right & left;
@ -360,7 +360,7 @@ static void edge(struct pt_regs *regs, unsigned int insn, unsigned int opf)
tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
regs->tstate = tstate | (ccr << 32UL);
}
};
}
}
static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
@ -392,7 +392,7 @@ static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
case ARRAY32_OPF:
rd_val <<= 2;
};
}
store_reg(regs, rd_val, RD(insn));
}
@ -577,7 +577,7 @@ static void pformat(struct pt_regs *regs, unsigned int insn, unsigned int opf)
*fpd_regaddr(f, RD(insn)) = rd_val;
break;
}
};
}
}
static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
@ -693,7 +693,7 @@ static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
*fpd_regaddr(f, RD(insn)) = rd_val;
break;
}
};
}
}
static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
@ -786,7 +786,7 @@ static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
rd_val |= 1 << i;
}
break;
};
}
maybe_flush_windows(0, 0, RD(insn), 0);
store_reg(regs, rd_val, RD(insn));
@ -885,7 +885,7 @@ int vis_emul(struct pt_regs *regs, unsigned int insn)
case BSHUFFLE_OPF:
bshuffle(regs, insn);
break;
};
}
regs->tpc = regs->tnpc;
regs->tnpc += 4;

2
arch/sparc/mm/fault_32.c
View File

@ -135,7 +135,7 @@ asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc,
default:
break;
};
}
memset(&regs, 0, sizeof (regs));
regs.pc = pc;

2
arch/sparc/mm/init_32.c
View File

@ -340,7 +340,7 @@ void __init paging_init(void)
prom_printf("paging_init: sparc_cpu_model = %d\n", sparc_cpu_model);
prom_printf("paging_init: Halting...\n");
prom_halt();
};
}
/* Initialize the protection map with non-constant, MMU dependent values. */
protection_map[0] = PAGE_NONE;

6
arch/sparc/mm/init_64.c
View File

@ -1625,7 +1625,7 @@ static void __init sun4v_ktsb_init(void)
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
break;
};
}
ktsb_descr[0].assoc = 1;
ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
@ -2266,7 +2266,7 @@ unsigned long pte_sz_bits(unsigned long sz)
return _PAGE_SZ512K_4V;
case 4 * 1024 * 1024:
return _PAGE_SZ4MB_4V;
};
}
} else {
switch (sz) {
case 8 * 1024:
@ -2278,7 +2278,7 @@ unsigned long pte_sz_bits(unsigned long sz)
return _PAGE_SZ512K_4U;
case 4 * 1024 * 1024:
return _PAGE_SZ4MB_4U;
};
}
}
}

4
arch/sparc/mm/srmmu.c
View File

@ -1665,7 +1665,7 @@ static void __init init_swift(void)
default:
srmmu_modtype = Swift_ok;
break;
};
}
BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
@ -2069,7 +2069,7 @@ static void __init get_srmmu_type(void)
/* Some other Cypress revision, assume a 605. */
init_cypress_605(mod_rev);
break;
};
}
return;
}

8
arch/sparc/mm/sun4c.c
View File

@ -318,7 +318,7 @@ void __init sun4c_probe_vac(void)
prom_printf("probe_vac: Didn't expect vac-linesize of %d, halting\n",
sun4c_vacinfo.linesize);
prom_halt();
};
}
sun4c_flush_all();
sun4c_enable_vac();
@ -364,7 +364,7 @@ static void __init patch_kernel_fault_handler(void)
prom_printf("Unhandled number of segmaps: %d\n",
num_segmaps);
prom_halt();
};
}
switch (num_contexts) {
case 8:
/* Default, nothing to do. */
@ -377,7 +377,7 @@ static void __init patch_kernel_fault_handler(void)
prom_printf("Unhandled number of contexts: %d\n",
num_contexts);
prom_halt();
};
}
if (sun4c_vacinfo.do_hwflushes != 0) {
PATCH_INSN(vac_hwflush_patch1_on, vac_hwflush_patch1);
@ -394,7 +394,7 @@ static void __init patch_kernel_fault_handler(void)
prom_printf("Impossible VAC linesize %d, halting...\n",
sun4c_vacinfo.linesize);
prom_halt();
};
}
}
}

6
arch/sparc/mm/tsb.c
View File

@ -180,7 +180,7 @@ static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsign
printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n",
current->comm, current->pid, tsb_bytes);
do_exit(SIGSEGV);
};
}
tte |= pte_sz_bits(page_sz);
if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
@ -215,7 +215,7 @@ static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsign
#endif
default:
BUG();
};
}
hp->assoc = 1;
hp->num_ttes = tsb_bytes / 16;
hp->ctx_idx = 0;
@ -230,7 +230,7 @@ static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsign
#endif
default:
BUG();
};
}
hp->tsb_base = tsb_paddr;
hp->resv = 0;
}

2
arch/sparc/prom/console_32.c
View File

@ -38,7 +38,7 @@ static int prom_nbputchar(const char *buf)
break;
default:
break;
};
}
restore_current();
spin_unlock_irqrestore(&prom_lock, flags);
return i; /* Ugh, we could spin forever on unsupported proms ;( */

2
arch/sparc/prom/init_32.c
View File

@ -53,7 +53,7 @@ void __init prom_init(struct linux_romvec *rp)
romvec->pv_romvers);
prom_halt();
break;
};
}
prom_rev = romvec->pv_plugin_revision;
prom_prev = romvec->pv_printrev;

2
arch/sparc/prom/mp.c
View File

@ -35,7 +35,7 @@ prom_startcpu(int cpunode, struct linux_prom_registers *ctable_reg, int ctx, cha
case PROM_V3:
ret = (*(romvec->v3_cpustart))(cpunode, (int) ctable_reg, ctx, pc);
break;
};
}
restore_current();
spin_unlock_irqrestore(&prom_lock, flags);

Some files were not shown because too many files have changed in this diff Show More