mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 03:40:25 +07:00
arm64: tegra: Device tree changes for v5.5-rc1
Adds support for DP and XUSB on various boards, enables SMMU support for more devices and fixes a couple of DTC warnings and inconsistencies that are reported at runtime. These changes along with some of the driver changes in other branches allow suspend/resume support on Tegra210 devices (e.g. Jetson TX1 and Jetson Nano). -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl29j9ATHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoebdEACKhpjhqqa/D8tXyU76THQozmTSM4tk k5yvth4lrO1tK5fytpLaVqZqoXUJzZK5ls2RWESzVemldtFbqtLaUmAPJwbdLiQ9 fo5sK47oekX8Mu3QsGejKExuHCklsRkr2FBlPX1dI8E1RTyiBexYqX1XYxFeSQ8L TJB0pNKK5HKoHGJztR/8dsJmKv5vKBnIBhBMRvP4wywdCY8Y2hZi6pqHQj8n1A4d wbr7BlZDiKMneLJ4YBdUj7N2Rwht7riB4CApLoE4+ev4QCMX1yG1g4FN/x7VQUAj ivL1mugGB+L7AYq5o1KVTUMJqau4xJ7vUqdwHf0lQ2odx29VOQ6PW9SjnaAReGDz BCyikUhvZL1nYZOahoaZf0D/jSqE9jUsgRgWBDMsjXIQN1pEo0Fu1bEhwrINam0j cWTEHobQ/L6fKO4gQdE8DdvCdWkL0kysC+afUrI3tiTTHKKpCKuvU6xwMiql+GuB 45UZB7pb8QTBVNSque27OBbPXpIOxc7kKjox5JjsP85LFHpRUREI/knx3Xf29m4Q ZjwadddS2nfP1o7eC2U5KjjhXYfxBPa6yvhPrtoKsuRfLCclKFEKjQfRvP6/NfdE 00Ic8MyHdr1xlyIb05BUXZHiNGWnwFgqDqwDVZ8RIzrEdz7J/o5TFI11Vw8GrjW5 r1yo8onHqoJVzA== =NTCt -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.5-rc1 Adds support for DP and XUSB on various boards, enables SMMU support for more devices and fixes a couple of DTC warnings and inconsistencies that are reported at runtime. These changes along with some of the driver changes in other branches allow suspend/resume support on Tegra210 devices (e.g. Jetson TX1 and Jetson Nano). * tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits) arm64: tegra: Add Jetson Nano SC7 timings arm64: tegra: Add Jetson TX1 SC7 timings arm64: tegra: Enable wake from deep sleep on RTC alarm arm64: tegra: Add PMU on Tegra210 arm64: tegra: Add blank lines for better readability arm64: tegra: Enable DisplayPort on Jetson AGX Xavier arm64: tegra: p2888: Rename regulators for consistency arm64: tegra: Enable DP support on Jetson TX2 arm64: tegra: Fix compatible for SOR1 arm64: tegra: Enable DP support on Jetson Nano arm64: tegra: Add SOR0_OUT clock on Tegra210 arm64: tegra: Assume no CLKREQ presence by default arm64: tegra: Enable SMMU for VIC on Tegra186 arm64: tegra: Enable XUSB host controller on Jetson TX2 arm64: tegra: Enable SMMU for XUSB host on Tegra186 arm64: tegra: Enable XUSB pad controller on Jetson TX2 arm64: tegra: Add ethernet alias on Jetson AGX Xavier arm64: tegra: Fix compatible string for EQOS on Tegra194 arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM arm64: tegra: Fix base address for SOR1 on Tegra194 ... Link: https://lore.kernel.org/r/20191102144521.3863321-8-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
fc711fdf06
@ -115,7 +115,7 @@ hda@3510000 {
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};
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padctl@3520000 {
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status = "disabled";
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status = "okay";
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avdd-pll-erefeut-supply = <&vdd_1v8_pll>;
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avdd-usb-supply = <&vdd_3v3_sys>;
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@ -193,7 +193,7 @@ usb3-0 {
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};
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usb@3530000 {
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status = "disabled";
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status = "okay";
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phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
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<&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
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@ -253,10 +253,14 @@ dsi@15300000 {
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status = "disabled";
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};
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/* DP on E3320 */
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sor@15540000 {
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status = "disabled";
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status = "okay";
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nvidia,dpaux = <&dpaux1>;
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avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
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vdd-hdmi-dp-pll = <&vdd_1v8_ap>;
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nvidia,dpaux = <&dpaux>;
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};
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sor@15580000 {
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@ -525,6 +525,7 @@ usb@3530000 {
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<0x0 0x03538000 0x0 0x1000>;
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reg-names = "hcd", "fpci";
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iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
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@ -1018,6 +1019,7 @@ vic@15340000 {
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reset-names = "vic";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
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iommus = <&smmu TEGRA186_SID_VIC>;
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};
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dsib: dsi@15400000 {
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@ -1060,7 +1062,7 @@ sor0: sor@15540000 {
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};
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sor1: sor@15580000 {
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compatible = "nvidia,tegra186-sor1";
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compatible = "nvidia,tegra186-sor";
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reg = <0x15580000 0x10000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SOR1>,
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@ -8,17 +8,18 @@ / {
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compatible = "nvidia,p2888", "nvidia,tegra194";
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aliases {
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sdhci0 = "/cbb/sdhci@3460000";
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sdhci1 = "/cbb/sdhci@3400000";
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ethernet0 = "/cbb@0/ethernet@2490000";
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sdhci0 = "/cbb@0/sdhci@3460000";
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sdhci1 = "/cbb@0/sdhci@3400000";
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serial0 = &tcu;
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i2c0 = "/bpmp/i2c";
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i2c1 = "/cbb/i2c@3160000";
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i2c2 = "/cbb/i2c@c240000";
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i2c3 = "/cbb/i2c@3180000";
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i2c4 = "/cbb/i2c@3190000";
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i2c5 = "/cbb/i2c@31c0000";
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i2c6 = "/cbb/i2c@c250000";
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i2c7 = "/cbb/i2c@31e0000";
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i2c1 = "/cbb@0/i2c@3160000";
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i2c2 = "/cbb@0/i2c@c240000";
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i2c3 = "/cbb@0/i2c@3180000";
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i2c4 = "/cbb@0/i2c@3190000";
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i2c5 = "/cbb@0/i2c@31c0000";
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i2c6 = "/cbb@0/i2c@c250000";
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i2c7 = "/cbb@0/i2c@31e0000";
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};
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chosen {
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@ -26,7 +27,7 @@ chosen {
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stdout-path = "serial0:115200n8";
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};
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cbb {
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cbb@0 {
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ethernet@2490000 {
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status = "okay";
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@ -168,7 +169,7 @@ regulators {
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in-ldo7-8-supply = <&vdd_1v8ls>;
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vdd_1v0: sd0 {
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regulator-name = "VDD_1V0";
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regulator-name = "VDDIO_SYS_1V0";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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@ -176,7 +177,7 @@ vdd_1v0: sd0 {
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};
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vdd_1v8hs: sd1 {
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regulator-name = "VDD_1V8HS";
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regulator-name = "VDDIO_SYS_1V8HS";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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@ -184,7 +185,7 @@ vdd_1v8hs: sd1 {
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};
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vdd_1v8ls: sd2 {
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regulator-name = "VDD_1V8LS";
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regulator-name = "VDDIO_SYS_1V8LS";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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@ -192,7 +193,7 @@ vdd_1v8ls: sd2 {
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};
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vdd_1v8ao: sd3 {
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regulator-name = "VDD_1V8AO";
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regulator-name = "VDDIO_AO_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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@ -216,7 +217,7 @@ ldo0 {
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};
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ldo2 {
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regulator-name = "VDD_AO_3V3";
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regulator-name = "VDDIO_AO_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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@ -242,7 +243,7 @@ ldo6 {
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};
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ldo7 {
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regulator-name = "VDD_CSI_1V2";
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regulator-name = "AVDD_CSI_1V2";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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@ -309,9 +310,8 @@ vdd_12v_pcie: regulator@3 {
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regulator-name = "VDD_12V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
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gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
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regulator-boot-on;
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enable-active-low;
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};
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};
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};
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@ -10,8 +10,8 @@ / {
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model = "NVIDIA Jetson AGX Xavier Developer Kit";
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compatible = "nvidia,p2972-0000", "nvidia,tegra194";
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cbb {
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aconnect {
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cbb@0 {
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aconnect@2900000 {
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status = "okay";
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dma-controller@2930000 {
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@ -46,10 +46,39 @@ display-hub@15200000 {
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status = "okay";
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};
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dpaux@155c0000 {
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status = "okay";
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};
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dpaux@155d0000 {
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status = "okay";
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};
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dpaux@155e0000 {
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status = "okay";
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};
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/* DP0 */
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sor@15b00000 {
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status = "okay";
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avdd-io-hdmi-dp-supply = <&vdd_1v0>;
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vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
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nvidia,dpaux = <&dpaux0>;
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};
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/* DP1 */
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sor@15b40000 {
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status = "okay";
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avdd-io-hdmi-dp-supply = <&vdd_1v0>;
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vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;
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nvidia,dpaux = <&dpaux1>;
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};
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/* HDMI */
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sor@15b80000 {
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status = "okay";
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@ -15,7 +15,7 @@ / {
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#size-cells = <2>;
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/* control backbone */
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cbb {
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cbb@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -39,7 +39,8 @@ gpio: gpio@2200000 {
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};
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ethernet@2490000 {
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compatible = "nvidia,tegra186-eqos",
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compatible = "nvidia,tegra194-eqos",
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"nvidia,tegra186-eqos",
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"snps,dwc-qos-ethernet-4.10";
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reg = <0x02490000 0x10000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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@ -60,7 +61,7 @@ ethernet@2490000 {
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snps,rxpbl = <8>;
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};
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aconnect {
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aconnect@2900000 {
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compatible = "nvidia,tegra194-aconnect",
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"nvidia,tegra210-aconnect";
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clocks = <&bpmp TEGRA194_CLK_APE>,
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@ -1078,7 +1079,7 @@ sor0: sor@15b00000 {
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sor1: sor@15b40000 {
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compatible = "nvidia,tegra194-sor";
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reg = <0x155c0000 0x40000>;
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reg = <0x15b40000 0x40000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
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<&bpmp TEGRA194_CLK_SOR1_OUT>,
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@ -1185,7 +1186,6 @@ pcie@14100000 {
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nvidia,bpmp = <&bpmp 1>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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@ -1231,7 +1231,6 @@ pcie@14120000 {
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nvidia,bpmp = <&bpmp 2>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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@ -1277,7 +1276,6 @@ pcie@14140000 {
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nvidia,bpmp = <&bpmp 3>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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@ -1323,7 +1321,6 @@ pcie@14160000 {
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nvidia,bpmp = <&bpmp 4>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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@ -1369,7 +1366,6 @@ pcie@14180000 {
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nvidia,bpmp = <&bpmp 0>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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@ -1419,7 +1415,6 @@ pcie@141a0000 {
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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@ -1478,60 +1473,192 @@ cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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cpu0_0: cpu@0 {
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compatible = "nvidia,tegra194-carmel";
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device_type = "cpu";
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reg = <0x10000>;
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reg = <0x000>;
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enable-method = "psci";
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2c_0>;
|
||||
};
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||||
cpu@1 {
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||||
cpu0_1: cpu@1 {
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||||
compatible = "nvidia,tegra194-carmel";
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||||
device_type = "cpu";
|
||||
reg = <0x10001>;
|
||||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_0>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
cpu1_0: cpu@100 {
|
||||
compatible = "nvidia,tegra194-carmel";
|
||||
device_type = "cpu";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_1>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
cpu1_1: cpu@101 {
|
||||
compatible = "nvidia,tegra194-carmel";
|
||||
device_type = "cpu";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_1>;
|
||||
};
|
||||
|
||||
cpu@4 {
|
||||
cpu2_0: cpu@200 {
|
||||
compatible = "nvidia,tegra194-carmel";
|
||||
device_type = "cpu";
|
||||
reg = <0x200>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_2>;
|
||||
};
|
||||
|
||||
cpu@5 {
|
||||
cpu2_1: cpu@201 {
|
||||
compatible = "nvidia,tegra194-carmel";
|
||||
device_type = "cpu";
|
||||
reg = <0x201>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_2>;
|
||||
};
|
||||
|
||||
cpu@6 {
|
||||
cpu3_0: cpu@300 {
|
||||
compatible = "nvidia,tegra194-carmel";
|
||||
device_type = "cpu";
|
||||
reg = <0x10300>;
|
||||
reg = <0x300>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_3>;
|
||||
};
|
||||
|
||||
cpu@7 {
|
||||
cpu3_1: cpu@301 {
|
||||
compatible = "nvidia,tegra194-carmel";
|
||||
device_type = "cpu";
|
||||
reg = <0x10301>;
|
||||
reg = <0x301>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <131072>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2c_3>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0_0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu0_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu1_0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&cpu2_0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu2_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster3 {
|
||||
core0 {
|
||||
cpu = <&cpu3_0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu3_1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
l2c_0: l2-cache0 {
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l2c_1: l2-cache1 {
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l2c_2: l2-cache2 {
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l2c_3: l2-cache3 {
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l3c: l3-cache {
|
||||
cache-size = <4194304>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <4096>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -279,6 +279,13 @@ eeprom@50 {
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
|
||||
@ -1612,7 +1612,7 @@ vdd_hdmi: regulator@10 {
|
||||
regulator-name = "VDD_HDMI_5V0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&exp1 12 GPIO_ACTIVE_LOW>;
|
||||
gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
|
||||
@ -64,6 +64,16 @@ dpaux@54040000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sor@54540000 {
|
||||
status = "okay";
|
||||
|
||||
avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
|
||||
vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
|
||||
|
||||
nvidia,xbar-cfg = <2 1 0 3 4>;
|
||||
nvidia,dpaux = <&dpaux>;
|
||||
};
|
||||
|
||||
sor@54580000 {
|
||||
status = "okay";
|
||||
|
||||
@ -76,6 +86,10 @@ sor@54580000 {
|
||||
GPIO_ACTIVE_LOW>;
|
||||
nvidia,xbar-cfg = <0 1 2 3 4>;
|
||||
};
|
||||
|
||||
dpaux@545c0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpu@57000000 {
|
||||
@ -382,6 +396,13 @@ avdd_1v05: ldo8 {
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
hda@70030000 {
|
||||
@ -680,5 +701,19 @@ vdd_gpu: regulator@6 {
|
||||
enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
|
||||
avdd_io_edp_1v05: regulator@7 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <7>;
|
||||
|
||||
regulator-name = "AVDD_IO_EDP_1V05";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
|
||||
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
vin-supply = <&avdd_1v05_pll>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -254,10 +254,11 @@ sor@54540000 {
|
||||
reg = <0x0 0x54540000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
|
||||
<&tegra_car TEGRA210_CLK_SOR0_OUT>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_DP>,
|
||||
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
|
||||
clock-names = "sor", "parent", "dp", "safe";
|
||||
clock-names = "sor", "out", "parent", "dp", "safe";
|
||||
resets = <&tegra_car 182>;
|
||||
reset-names = "sor";
|
||||
pinctrl-0 = <&state_dpaux_aux>;
|
||||
@ -768,7 +769,8 @@ spi@7000da00 {
|
||||
rtc@7000e000 {
|
||||
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x0 0x7000e000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
@ -778,6 +780,8 @@ pmc: pmc@7000e400 {
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
@ -1438,6 +1442,16 @@ L2: l2-cache {
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
|
||||
&{/cpus/cpu@2} &{/cpus/cpu@3}>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
@ -1457,7 +1471,9 @@ soctherm: thermal-sensor@700e2000 {
|
||||
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
|
||||
0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
|
||||
reg-names = "soctherm-reg", "car-reg";
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "thermal", "edp";
|
||||
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
|
||||
<&tegra_car TEGRA210_CLK_SOC_THERM>;
|
||||
clock-names = "tsensor", "soctherm";
|
||||
@ -1504,6 +1520,7 @@ map0 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mem {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
@ -1526,6 +1543,7 @@ cooling-maps {
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
gpu {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <0>;
|
||||
@ -1554,6 +1572,7 @@ map0 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pllx {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user