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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[MIPS] Atlas: update interrupt handling
The following change updates the Atlas interrupt handling to match that of Malta. Tested with a 5Kc and a 34Kf successfully. Signed-off-by: Maciej W. Rozycki <macro@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
Ralf Baechle
parent
3ee24e1b1e
commit
fc095a9021
@ -1,6 +1,8 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 1999, 2000, 2006 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* ########################################################################
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*
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@ -25,17 +27,20 @@
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*/
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#include <linux/compiler.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <asm/irq.h>
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#include <asm/gdb-stub.h>
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#include <asm/io.h>
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#include <asm/irq_cpu.h>
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#include <asm/msc01_ic.h>
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#include <asm/mips-boards/atlas.h>
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#include <asm/mips-boards/atlasint.h>
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#include <asm/gdb-stub.h>
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#include <asm/mips-boards/generic.h>
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static struct atlas_ictrl_regs *atlas_hw0_icregs;
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@ -47,13 +52,13 @@ static struct atlas_ictrl_regs *atlas_hw0_icregs;
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void disable_atlas_irq(unsigned int irq_nr)
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{
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atlas_hw0_icregs->intrsten = (1 << (irq_nr-ATLASINT_BASE));
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atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
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iob();
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}
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void enable_atlas_irq(unsigned int irq_nr)
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{
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atlas_hw0_icregs->intseten = (1 << (irq_nr-ATLASINT_BASE));
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atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
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iob();
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}
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@ -107,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
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if (unlikely(int_status == 0))
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return;
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irq = ATLASINT_BASE + ls1bit32(int_status);
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irq = ATLAS_INT_BASE + ls1bit32(int_status);
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DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
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@ -161,15 +166,14 @@ static inline unsigned int irq_ffs(unsigned int pending)
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}
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/*
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* IRQs on the Atlas board look basically (barring software IRQs which we
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* don't use at all and all external interrupt sources are combined together
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* on hardware interrupt 0 (MIPS IRQ 2)) like:
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* IRQs on the Atlas board look basically like (all external interrupt
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* sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
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*
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* MIPS IRQ Source
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Combined hardware interrupt (hw0)
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* 0 Software 0 (reschedule IPI on MT)
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* 1 Software 1 (remote call IPI on MT)
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* 2 Combined Atlas hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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@ -179,7 +183,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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* Lowest ---- Software 0
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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@ -193,17 +197,19 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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if (irq == MIPSCPU_INT_ATLAS)
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atlas_hw0_irqdispatch(regs);
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else if (irq > 0)
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else if (irq >= 0)
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do_IRQ(MIPSCPU_INT_BASE + irq, regs);
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else
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spurious_interrupt(regs);
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}
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void __init arch_init_irq(void)
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static inline void init_atlas_irqs (int base)
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{
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int i;
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atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *));
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atlas_hw0_icregs = (struct atlas_ictrl_regs *)
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ioremap(ATLAS_ICTRL_REGS_BASE,
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sizeof(struct atlas_ictrl_regs *));
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/*
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* Mask out all interrupt by writing "1" to all bit position in
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@ -211,7 +217,7 @@ void __init arch_init_irq(void)
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*/
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atlas_hw0_icregs->intrsten = 0xffffffff;
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for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) {
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for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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@ -219,3 +225,62 @@ void __init arch_init_irq(void)
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spin_lock_init(&irq_desc[i].lock);
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}
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}
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static struct irqaction atlasirq = {
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.handler = no_action,
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.name = "Atlas cascade"
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};
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msc_irqmap_t __initdata msc_irqmap[] = {
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{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
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};
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int __initdata msc_nr_irqs = sizeof(msc_irqmap) / sizeof(*msc_irqmap);
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msc_irqmap_t __initdata msc_eicirqmap[] = {
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{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_ATLAS, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
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};
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int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap) / sizeof(*msc_eicirqmap);
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void __init arch_init_irq(void)
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{
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init_atlas_irqs(ATLAS_INT_BASE);
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if (!cpu_has_veic)
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mips_cpu_irq_init(MIPSCPU_INT_BASE);
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_FPGA3:
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case MIPS_REVISION_CORID_CORE_24K:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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if (cpu_has_veic)
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init_msc_irqs (MSC01E_INT_BASE,
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msc_eicirqmap, msc_nr_eicirqs);
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else
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init_msc_irqs (MSC01C_INT_BASE,
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msc_irqmap, msc_nr_irqs);
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}
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if (cpu_has_veic) {
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set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
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setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
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} else if (cpu_has_vint) {
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set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
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&atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
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#else /* Not SMTC */
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setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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} else
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setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
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}
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@ -77,7 +77,7 @@ static void __init serial_init(void)
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#else
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s.iobase = ATLAS_UART_REGS_BASE+3;
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#endif
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s.irq = ATLASINT_UART;
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s.irq = ATLAS_INT_UART;
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s.uartclk = ATLAS_BASE_BAUD * 16;
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s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
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s.iotype = UPIO_PORT;
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@ -41,8 +41,13 @@
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/prom.h>
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#ifdef CONFIG_MIPS_ATLAS
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#include <asm/mips-boards/atlasint.h>
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#endif
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#ifdef CONFIG_MIPS_MALTA
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#include <asm/mips-boards/maltaint.h>
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#include <asm/mc146818-time.h>
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#endif
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unsigned long cpu_khz;
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@ -21,16 +21,16 @@
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#include <asm/mips-boards/atlasint.h>
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#define PCIA ATLASINT_PCIA
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#define PCIB ATLASINT_PCIB
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#define PCIC ATLASINT_PCIC
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#define PCID ATLASINT_PCID
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#define INTA ATLASINT_INTA
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#define INTB ATLASINT_INTB
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#define ETH ATLASINT_ETH
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#define INTC ATLASINT_INTC
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#define SCSI ATLASINT_SCSI
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#define INTD ATLASINT_INTD
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#define PCIA ATLAS_INT_PCIA
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#define PCIB ATLAS_INT_PCIB
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#define PCIC ATLAS_INT_PCIC
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#define PCID ATLAS_INT_PCID
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#define INTA ATLAS_INT_INTA
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#define INTB ATLAS_INT_INTB
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#define ETH ATLAS_INT_ETH
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#define INTC ATLAS_INT_INTC
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#define SCSI ATLAS_INT_SCSI
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#define INTD ATLAS_INT_INTD
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static char irq_tab[][5] __initdata = {
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/* INTA INTB INTC INTD */
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@ -33,7 +33,7 @@
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#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8)
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#define RTC_IO_EXTENT 0x100
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#define RTC_IOMAPPED 0
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#define RTC_IRQ ATLASINT_RTC
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#define RTC_IRQ ATLAS_INT_RTC
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static inline unsigned char CMOS_READ(unsigned long addr)
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{
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@ -1,6 +1,7 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* ########################################################################
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*
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@ -25,41 +26,88 @@
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#ifndef _MIPS_ATLASINT_H
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#define _MIPS_ATLASINT_H
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#define ATLASINT_BASE 1
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#define ATLASINT_UART (ATLASINT_BASE+0)
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#define ATLASINT_TIM0 (ATLASINT_BASE+1)
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#define ATLASINT_RES2 (ATLASINT_BASE+2)
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#define ATLASINT_RES3 (ATLASINT_BASE+3)
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#define ATLASINT_RTC (ATLASINT_BASE+4)
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#define ATLASINT_COREHI (ATLASINT_BASE+5)
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#define ATLASINT_CORELO (ATLASINT_BASE+6)
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#define ATLASINT_RES7 (ATLASINT_BASE+7)
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#define ATLASINT_PCIA (ATLASINT_BASE+8)
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#define ATLASINT_PCIB (ATLASINT_BASE+9)
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#define ATLASINT_PCIC (ATLASINT_BASE+10)
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#define ATLASINT_PCID (ATLASINT_BASE+11)
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#define ATLASINT_ENUM (ATLASINT_BASE+12)
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#define ATLASINT_DEG (ATLASINT_BASE+13)
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#define ATLASINT_ATXFAIL (ATLASINT_BASE+14)
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#define ATLASINT_INTA (ATLASINT_BASE+15)
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#define ATLASINT_INTB (ATLASINT_BASE+16)
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#define ATLASINT_ETH ATLASINT_INTB
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#define ATLASINT_INTC (ATLASINT_BASE+17)
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#define ATLASINT_SCSI ATLASINT_INTC
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#define ATLASINT_INTD (ATLASINT_BASE+18)
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#define ATLASINT_SERR (ATLASINT_BASE+19)
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#define ATLASINT_RES20 (ATLASINT_BASE+20)
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#define ATLASINT_RES21 (ATLASINT_BASE+21)
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#define ATLASINT_RES22 (ATLASINT_BASE+22)
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#define ATLASINT_RES23 (ATLASINT_BASE+23)
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#define ATLASINT_RES24 (ATLASINT_BASE+24)
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#define ATLASINT_RES25 (ATLASINT_BASE+25)
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#define ATLASINT_RES26 (ATLASINT_BASE+26)
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#define ATLASINT_RES27 (ATLASINT_BASE+27)
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#define ATLASINT_RES28 (ATLASINT_BASE+28)
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#define ATLASINT_RES29 (ATLASINT_BASE+29)
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#define ATLASINT_RES30 (ATLASINT_BASE+30)
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#define ATLASINT_RES31 (ATLASINT_BASE+31)
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#define ATLASINT_END (ATLASINT_BASE+31)
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/*
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* Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
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*/
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#define MIPSCPU_INT_BASE 0
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/* CPU interrupt offsets */
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#define MIPSCPU_INT_SW0 0
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#define MIPSCPU_INT_SW1 1
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#define MIPSCPU_INT_MB0 2
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#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0
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#define MIPSCPU_INT_MB1 3
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#define MIPSCPU_INT_MB2 4
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#define MIPSCPU_INT_MB3 5
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#define MIPSCPU_INT_MB4 6
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#define MIPSCPU_INT_CPUCTR 7
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/*
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* Interrupts 8..39 are used for Atlas interrupt controller interrupts
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*/
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#define ATLAS_INT_BASE 8
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#define ATLAS_INT_UART (ATLAS_INT_BASE + 0)
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#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1)
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#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2)
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#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3)
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#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4)
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#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5)
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#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6)
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#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7)
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#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8)
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#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9)
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#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10)
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#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11)
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#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12)
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#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13)
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#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14)
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#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15)
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#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16)
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#define ATLAS_INT_ETH ATLAS_INT_INTB
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#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17)
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#define ATLAS_INT_SCSI ATLAS_INT_INTC
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#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18)
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#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19)
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#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20)
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#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21)
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#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22)
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#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23)
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#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24)
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#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25)
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#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26)
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#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27)
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#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28)
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#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29)
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#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30)
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#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31)
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#define ATLAS_INT_END (ATLAS_INT_BASE + 31)
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/*
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* Interrupts 64..127 are used for Soc-it Classic interrupts
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*/
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#define MSC01C_INT_BASE 64
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/* SOC-it Classic interrupt offsets */
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#define MSC01C_INT_TMR 0
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#define MSC01C_INT_PCI 1
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/*
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* Interrupts 64..127 are used for Soc-it EIC interrupts
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*/
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#define MSC01E_INT_BASE 64
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/* SOC-it EIC interrupt offsets */
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#define MSC01E_INT_SW0 1
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#define MSC01E_INT_SW1 2
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#define MSC01E_INT_MB0 3
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#define MSC01E_INT_ATLAS MSC01E_INT_MB0
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#define MSC01E_INT_MB1 4
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#define MSC01E_INT_MB2 5
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#define MSC01E_INT_MB3 6
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#define MSC01E_INT_MB4 7
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#define MSC01E_INT_TMR 8
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#define MSC01E_INT_PCI 9
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#define MSC01E_INT_PERFCTR 10
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#define MSC01E_INT_CPUCTR 11
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#endif /* !(_MIPS_ATLASINT_H) */
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