mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 23:16:44 +07:00
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
Jeff Kirsher says: ==================== Intel Wired LAN Driver Updates This series contains updates to i40e only. Jacob provides a i40e patch to get 1588 work correctly by separating TSYNVALID and TSYNINDX fields in the receive descriptor. Jesse provides several i40e patches, first to correct the checking of the multi-bit state. The hash is reported correctly in the RSS field if and only if the filter status is 3. Other values of the filter status mean different things and we should not depend on a bitwise result. Then provides a patch to enable a couple of workarounds based on revision ID that allow the driver to work more fully on early hardware. Shannon provides several i40e patches as well. First sets the media type in the hardware structure based on the external connection type. Then provides a patch to only setup the rings that will be used. Lastly provides a fix where the TESTING state was still set when exiting the ethtool diagnostics. Kevin Scott provides one i40e patch to add a new flag to the i40e_add_veb() which allows the driver to request the hardware to filter on layer 2 parameters. Anjali provides four i40e patches, first refactors the reset code in order to re-size queues and vectors while the interface is still up. Then provides a patch to enable all PCTYPEs expect FCoE for RSS. Adds a message to notify the user of how many VFs are initialized on each port. Lastly adds a new variable to track the number of PF instances, this is a global counter on purpose so that each PF loaded has a unique ID. Catherine bumps the driver version. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
fbec370638
@ -61,6 +61,7 @@
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#define I40E_BASE_VSI_SEID 512
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#define I40E_BASE_VEB_SEID 288
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#define I40E_MAX_VEB 16
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#define I40E_MAX_NPAR_QPS 32
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#define I40E_MAX_NUM_DESCRIPTORS 4096
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#define I40E_MAX_REGISTER 0x0038FFFF
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@ -275,6 +276,8 @@ struct i40e_pf {
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struct dentry *i40e_dbg_pf;
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#endif /* CONFIG_DEBUG_FS */
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u16 instance; /* A unique number per i40e_pf instance in the system */
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/* sr-iov config info */
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struct i40e_vf *vf;
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int num_alloc_vfs; /* actual number of VFs allocated */
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@ -266,6 +266,54 @@ i40e_status i40e_validate_mac_addr(u8 *mac_addr)
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return status;
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}
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/**
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* i40e_get_media_type - Gets media type
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* @hw: pointer to the hardware structure
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**/
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static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
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{
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enum i40e_media_type media;
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switch (hw->phy.link_info.phy_type) {
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case I40E_PHY_TYPE_10GBASE_SR:
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case I40E_PHY_TYPE_10GBASE_LR:
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case I40E_PHY_TYPE_40GBASE_SR4:
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case I40E_PHY_TYPE_40GBASE_LR4:
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media = I40E_MEDIA_TYPE_FIBER;
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break;
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case I40E_PHY_TYPE_100BASE_TX:
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case I40E_PHY_TYPE_1000BASE_T:
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case I40E_PHY_TYPE_10GBASE_T:
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media = I40E_MEDIA_TYPE_BASET;
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break;
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case I40E_PHY_TYPE_10GBASE_CR1_CU:
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case I40E_PHY_TYPE_40GBASE_CR4_CU:
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case I40E_PHY_TYPE_10GBASE_CR1:
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case I40E_PHY_TYPE_40GBASE_CR4:
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case I40E_PHY_TYPE_10GBASE_SFPP_CU:
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media = I40E_MEDIA_TYPE_DA;
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break;
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case I40E_PHY_TYPE_1000BASE_KX:
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case I40E_PHY_TYPE_10GBASE_KX4:
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case I40E_PHY_TYPE_10GBASE_KR:
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case I40E_PHY_TYPE_40GBASE_KR4:
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media = I40E_MEDIA_TYPE_BACKPLANE;
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break;
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case I40E_PHY_TYPE_SGMII:
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case I40E_PHY_TYPE_XAUI:
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case I40E_PHY_TYPE_XFI:
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case I40E_PHY_TYPE_XLAUI:
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case I40E_PHY_TYPE_XLPPI:
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default:
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media = I40E_MEDIA_TYPE_UNKNOWN;
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break;
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}
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return media;
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}
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#define I40E_PF_RESET_WAIT_COUNT_A0 200
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#define I40E_PF_RESET_WAIT_COUNT 10
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/**
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* i40e_pf_reset - Reset the PF
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* @hw: pointer to the hardware structure
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@ -275,7 +323,7 @@ i40e_status i40e_validate_mac_addr(u8 *mac_addr)
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**/
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i40e_status i40e_pf_reset(struct i40e_hw *hw)
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{
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u32 wait_cnt = 0;
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u32 cnt = 0;
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u32 reg = 0;
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u32 grst_del;
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@ -285,7 +333,7 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw)
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*/
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grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
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>> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
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for (wait_cnt = 0; wait_cnt < grst_del + 2; wait_cnt++) {
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for (cnt = 0; cnt < grst_del + 2; cnt++) {
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reg = rd32(hw, I40E_GLGEN_RSTAT);
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if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
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break;
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@ -306,11 +354,15 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw)
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/* If there was a Global Reset in progress when we got here,
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* we don't need to do the PF Reset
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*/
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if (!wait_cnt) {
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if (!cnt) {
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if (hw->revision_id == 0)
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cnt = I40E_PF_RESET_WAIT_COUNT_A0;
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else
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cnt = I40E_PF_RESET_WAIT_COUNT;
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reg = rd32(hw, I40E_PFGEN_CTRL);
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wr32(hw, I40E_PFGEN_CTRL,
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(reg | I40E_PFGEN_CTRL_PFSWR_MASK));
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for (wait_cnt = 0; wait_cnt < 10; wait_cnt++) {
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for (; cnt; cnt--) {
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reg = rd32(hw, I40E_PFGEN_CTRL);
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if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
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break;
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@ -339,7 +391,13 @@ void i40e_clear_pxe_mode(struct i40e_hw *hw)
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/* Clear single descriptor fetch/write-back mode */
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reg = rd32(hw, I40E_GLLAN_RCTL_0);
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wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
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if (hw->revision_id == 0) {
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/* As a work around clear PXE_MODE instead of setting it */
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wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
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} else {
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wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
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}
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}
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/**
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@ -499,6 +557,7 @@ i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
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/* update link status */
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hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
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hw->phy.media_type = i40e_get_media_type(hw);
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hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
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hw_link_info->link_info = resp->link_info;
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hw_link_info->an_info = resp->an_info;
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@ -877,6 +936,7 @@ bool i40e_get_link_status(struct i40e_hw *hw)
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* @downlink_seid: the VSI SEID
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* @enabled_tc: bitmap of TCs to be enabled
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* @default_port: true for default port VSI, false for control port
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* @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
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* @veb_seid: pointer to where to put the resulting VEB SEID
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* @cmd_details: pointer to command details structure or NULL
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*
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@ -885,7 +945,8 @@ bool i40e_get_link_status(struct i40e_hw *hw)
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**/
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i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
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u16 downlink_seid, u8 enabled_tc,
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bool default_port, u16 *veb_seid,
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bool default_port, bool enable_l2_filtering,
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u16 *veb_seid,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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@ -911,6 +972,10 @@ i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
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veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
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else
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veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
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if (enable_l2_filtering)
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veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
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cmd->veb_flags = cpu_to_le16(veb_flags);
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status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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@ -211,6 +211,10 @@ static int i40e_get_settings(struct net_device *netdev,
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ecmd->supported |= SUPPORTED_TP;
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ecmd->advertising |= ADVERTISED_TP;
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ecmd->port = PORT_TP;
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} else if (hw->phy.media_type == I40E_MEDIA_TYPE_DA) {
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ecmd->supported |= SUPPORTED_FIBRE;
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ecmd->advertising |= ADVERTISED_FIBRE;
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ecmd->port = PORT_DA;
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} else {
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ecmd->supported |= SUPPORTED_FIBRE;
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ecmd->advertising |= ADVERTISED_FIBRE;
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@ -702,8 +706,12 @@ static int i40e_get_ts_info(struct net_device *dev,
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return ethtool_op_get_ts_info(dev, info);
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}
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static int i40e_link_test(struct i40e_pf *pf, u64 *data)
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static int i40e_link_test(struct net_device *netdev, u64 *data)
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{
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struct i40e_netdev_priv *np = netdev_priv(netdev);
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struct i40e_pf *pf = np->vsi->back;
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netdev_info(netdev, "link test\n");
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if (i40e_get_link_status(&pf->hw))
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*data = 0;
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else
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@ -712,30 +720,36 @@ static int i40e_link_test(struct i40e_pf *pf, u64 *data)
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return *data;
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}
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static int i40e_reg_test(struct i40e_pf *pf, u64 *data)
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static int i40e_reg_test(struct net_device *netdev, u64 *data)
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{
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i40e_status ret;
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struct i40e_netdev_priv *np = netdev_priv(netdev);
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struct i40e_pf *pf = np->vsi->back;
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ret = i40e_diag_reg_test(&pf->hw);
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*data = ret;
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netdev_info(netdev, "register test\n");
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*data = i40e_diag_reg_test(&pf->hw);
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return ret;
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i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
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return *data;
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}
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static int i40e_eeprom_test(struct i40e_pf *pf, u64 *data)
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static int i40e_eeprom_test(struct net_device *netdev, u64 *data)
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{
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i40e_status ret;
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struct i40e_netdev_priv *np = netdev_priv(netdev);
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struct i40e_pf *pf = np->vsi->back;
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ret = i40e_diag_eeprom_test(&pf->hw);
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*data = ret;
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netdev_info(netdev, "eeprom test\n");
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*data = i40e_diag_eeprom_test(&pf->hw);
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return ret;
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return *data;
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}
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static int i40e_intr_test(struct i40e_pf *pf, u64 *data)
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static int i40e_intr_test(struct net_device *netdev, u64 *data)
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{
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struct i40e_netdev_priv *np = netdev_priv(netdev);
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struct i40e_pf *pf = np->vsi->back;
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u16 swc_old = pf->sw_int_count;
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netdev_info(netdev, "interrupt test\n");
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wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
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(I40E_PFINT_DYN_CTL0_INTENA_MASK |
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I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
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@ -745,8 +759,9 @@ static int i40e_intr_test(struct i40e_pf *pf, u64 *data)
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return *data;
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}
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static int i40e_loopback_test(struct i40e_pf *pf, u64 *data)
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static int i40e_loopback_test(struct net_device *netdev, u64 *data)
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{
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netdev_info(netdev, "loopback test not implemented\n");
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*data = 0;
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return *data;
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@ -767,33 +782,25 @@ static void i40e_diag_test(struct net_device *netdev,
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/* Link test performed before hardware reset
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* so autoneg doesn't interfere with test result
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*/
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netdev_info(netdev, "link test starting\n");
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if (i40e_link_test(pf, &data[I40E_ETH_TEST_LINK]))
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if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
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eth_test->flags |= ETH_TEST_FL_FAILED;
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netdev_info(netdev, "register test starting\n");
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if (i40e_reg_test(pf, &data[I40E_ETH_TEST_REG]))
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if (i40e_reg_test(netdev, &data[I40E_ETH_TEST_REG]))
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eth_test->flags |= ETH_TEST_FL_FAILED;
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i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
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netdev_info(netdev, "eeprom test starting\n");
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if (i40e_eeprom_test(pf, &data[I40E_ETH_TEST_EEPROM]))
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if (i40e_eeprom_test(netdev, &data[I40E_ETH_TEST_EEPROM]))
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eth_test->flags |= ETH_TEST_FL_FAILED;
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i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
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netdev_info(netdev, "interrupt test starting\n");
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if (i40e_intr_test(pf, &data[I40E_ETH_TEST_INTR]))
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if (i40e_intr_test(netdev, &data[I40E_ETH_TEST_INTR]))
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eth_test->flags |= ETH_TEST_FL_FAILED;
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|
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i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
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netdev_info(netdev, "loopback test starting\n");
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if (i40e_loopback_test(pf, &data[I40E_ETH_TEST_LOOPBACK]))
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if (i40e_loopback_test(netdev, &data[I40E_ETH_TEST_LOOPBACK]))
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eth_test->flags |= ETH_TEST_FL_FAILED;
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|
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} else {
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netdev_info(netdev, "online test starting\n");
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/* Online tests */
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if (i40e_link_test(pf, &data[I40E_ETH_TEST_LINK]))
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if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
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eth_test->flags |= ETH_TEST_FL_FAILED;
|
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|
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/* Offline only tests, not run in online; pass by default */
|
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@ -801,9 +808,10 @@ static void i40e_diag_test(struct net_device *netdev,
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data[I40E_ETH_TEST_EEPROM] = 0;
|
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data[I40E_ETH_TEST_INTR] = 0;
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data[I40E_ETH_TEST_LOOPBACK] = 0;
|
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|
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clear_bit(__I40E_TESTING, &pf->state);
|
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}
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clear_bit(__I40E_TESTING, &pf->state);
|
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|
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netdev_info(netdev, "testing finished\n");
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}
|
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|
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static void i40e_get_wol(struct net_device *netdev,
|
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|
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@ -36,7 +36,7 @@ static const char i40e_driver_string[] =
|
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|
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#define DRV_VERSION_MAJOR 0
|
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#define DRV_VERSION_MINOR 3
|
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#define DRV_VERSION_BUILD 11
|
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#define DRV_VERSION_BUILD 12
|
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#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
|
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__stringify(DRV_VERSION_MINOR) "." \
|
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__stringify(DRV_VERSION_BUILD) DRV_KERN
|
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@ -574,10 +574,11 @@ static void i40e_update_veb_stats(struct i40e_veb *veb)
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i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
|
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veb->stat_offsets_loaded,
|
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&oes->tx_discards, &es->tx_discards);
|
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i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
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veb->stat_offsets_loaded,
|
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&oes->rx_unknown_protocol, &es->rx_unknown_protocol);
|
||||
|
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if (hw->revision_id > 0)
|
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i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
|
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veb->stat_offsets_loaded,
|
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&oes->rx_unknown_protocol,
|
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&es->rx_unknown_protocol);
|
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i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
|
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veb->stat_offsets_loaded,
|
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&oes->rx_bytes, &es->rx_bytes);
|
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@ -2240,7 +2241,10 @@ static int i40e_configure_rx_ring(struct i40e_ring *ring)
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rx_ctx.tphwdesc_ena = 1;
|
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rx_ctx.tphdata_ena = 1;
|
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rx_ctx.tphhead_ena = 1;
|
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rx_ctx.lrxqthresh = 2;
|
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if (hw->revision_id == 0)
|
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rx_ctx.lrxqthresh = 0;
|
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else
|
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rx_ctx.lrxqthresh = 2;
|
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rx_ctx.crcstrip = 1;
|
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rx_ctx.l2tsel = 1;
|
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rx_ctx.showiv = 1;
|
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@ -3021,6 +3025,9 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
|
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}
|
||||
}
|
||||
|
||||
if (hw->revision_id == 0)
|
||||
mdelay(50);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -4612,6 +4619,13 @@ static int i40e_get_capabilities(struct i40e_pf *pf)
|
||||
}
|
||||
} while (err);
|
||||
|
||||
if (pf->hw.revision_id == 0 && pf->hw.func_caps.npar_enable) {
|
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pf->hw.func_caps.num_msix_vectors += 1;
|
||||
pf->hw.func_caps.num_tx_qp =
|
||||
min_t(int, pf->hw.func_caps.num_tx_qp,
|
||||
I40E_MAX_NPAR_QPS);
|
||||
}
|
||||
|
||||
if (pf->hw.debug_mask & I40E_DEBUG_USER)
|
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dev_info(&pf->pdev->dev,
|
||||
"pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
|
||||
@ -4623,6 +4637,15 @@ static int i40e_get_capabilities(struct i40e_pf *pf)
|
||||
pf->hw.func_caps.num_tx_qp,
|
||||
pf->hw.func_caps.num_vsis);
|
||||
|
||||
#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
|
||||
+ pf->hw.func_caps.num_vfs)
|
||||
if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
|
||||
dev_info(&pf->pdev->dev,
|
||||
"got num_vsis %d, setting num_vsis to %d\n",
|
||||
pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
|
||||
pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -4693,22 +4716,20 @@ static void i40e_fdir_teardown(struct i40e_pf *pf)
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_handle_reset_warning - prep for the core to reset
|
||||
* i40e_prep_for_reset - prep for the core to reset
|
||||
* @pf: board private structure
|
||||
*
|
||||
* Close up the VFs and other things in prep for a Core Reset,
|
||||
* then get ready to rebuild the world.
|
||||
**/
|
||||
static void i40e_handle_reset_warning(struct i40e_pf *pf)
|
||||
* Close up the VFs and other things in prep for pf Reset.
|
||||
**/
|
||||
static int i40e_prep_for_reset(struct i40e_pf *pf)
|
||||
{
|
||||
struct i40e_driver_version dv;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
i40e_status ret;
|
||||
u32 v;
|
||||
|
||||
clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
|
||||
if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
|
||||
return;
|
||||
return 0;
|
||||
|
||||
dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
|
||||
|
||||
@ -4724,6 +4745,26 @@ static void i40e_handle_reset_warning(struct i40e_pf *pf)
|
||||
|
||||
i40e_shutdown_adminq(&pf->hw);
|
||||
|
||||
/* call shutdown HMC */
|
||||
ret = i40e_shutdown_lan_hmc(hw);
|
||||
if (ret) {
|
||||
dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
|
||||
clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_reset_and_rebuild - reset and rebuid using a saved config
|
||||
* @pf: board private structure
|
||||
**/
|
||||
static void i40e_reset_and_rebuild(struct i40e_pf *pf)
|
||||
{
|
||||
struct i40e_driver_version dv;
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
i40e_status ret;
|
||||
u32 v;
|
||||
|
||||
/* Now we wait for GRST to settle out.
|
||||
* We don't have to delete the VEBs or VSIs from the hw switch
|
||||
* because the reset will make them disappear.
|
||||
@ -4751,13 +4792,6 @@ static void i40e_handle_reset_warning(struct i40e_pf *pf)
|
||||
goto end_core_reset;
|
||||
}
|
||||
|
||||
/* call shutdown HMC */
|
||||
ret = i40e_shutdown_lan_hmc(hw);
|
||||
if (ret) {
|
||||
dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
|
||||
goto end_core_reset;
|
||||
}
|
||||
|
||||
ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
|
||||
hw->func_caps.num_rx_qp,
|
||||
pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
|
||||
@ -4850,6 +4884,22 @@ static void i40e_handle_reset_warning(struct i40e_pf *pf)
|
||||
clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
|
||||
* @pf: board private structure
|
||||
*
|
||||
* Close up the VFs and other things in prep for a Core Reset,
|
||||
* then get ready to rebuild the world.
|
||||
**/
|
||||
static void i40e_handle_reset_warning(struct i40e_pf *pf)
|
||||
{
|
||||
i40e_status ret;
|
||||
|
||||
ret = i40e_prep_for_reset(pf);
|
||||
if (!ret)
|
||||
i40e_reset_and_rebuild(pf);
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_handle_mdd_event
|
||||
* @pf: pointer to the pf structure
|
||||
@ -5025,6 +5075,39 @@ static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
|
||||
* @type: VSI pointer
|
||||
*
|
||||
* On error: returns error code (negative)
|
||||
* On success: returns 0
|
||||
**/
|
||||
static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi)
|
||||
{
|
||||
int size;
|
||||
int ret = 0;
|
||||
|
||||
/* allocate memory for both Tx and Rx ring pointers */
|
||||
size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
|
||||
vsi->tx_rings = kzalloc(size, GFP_KERNEL);
|
||||
if (!vsi->tx_rings)
|
||||
return -ENOMEM;
|
||||
vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
|
||||
|
||||
/* allocate memory for q_vector pointers */
|
||||
size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
|
||||
vsi->q_vectors = kzalloc(size, GFP_KERNEL);
|
||||
if (!vsi->q_vectors) {
|
||||
ret = -ENOMEM;
|
||||
goto err_vectors;
|
||||
}
|
||||
return ret;
|
||||
|
||||
err_vectors:
|
||||
kfree(vsi->tx_rings);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
|
||||
* @pf: board private structure
|
||||
@ -5037,8 +5120,6 @@ static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
struct i40e_vsi *vsi;
|
||||
int sz_vectors;
|
||||
int sz_rings;
|
||||
int vsi_idx;
|
||||
int i;
|
||||
|
||||
@ -5088,22 +5169,9 @@ static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
|
||||
if (ret)
|
||||
goto err_rings;
|
||||
|
||||
/* allocate memory for ring pointers */
|
||||
sz_rings = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
|
||||
vsi->tx_rings = kzalloc(sz_rings, GFP_KERNEL);
|
||||
if (!vsi->tx_rings) {
|
||||
ret = -ENOMEM;
|
||||
ret = i40e_vsi_alloc_arrays(vsi);
|
||||
if (ret)
|
||||
goto err_rings;
|
||||
}
|
||||
vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
|
||||
|
||||
/* allocate memory for q_vector pointers */
|
||||
sz_vectors = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
|
||||
vsi->q_vectors = kzalloc(sz_vectors, GFP_KERNEL);
|
||||
if (!vsi->q_vectors) {
|
||||
ret = -ENOMEM;
|
||||
goto err_vectors;
|
||||
}
|
||||
|
||||
/* Setup default MSIX irq handler for VSI */
|
||||
i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
|
||||
@ -5112,8 +5180,6 @@ static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
|
||||
ret = vsi_idx;
|
||||
goto unlock_pf;
|
||||
|
||||
err_vectors:
|
||||
kfree(vsi->tx_rings);
|
||||
err_rings:
|
||||
pf->next_vsi = i - 1;
|
||||
kfree(vsi);
|
||||
@ -5122,6 +5188,23 @@ static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
|
||||
* @type: VSI pointer
|
||||
*
|
||||
* On error: returns error code (negative)
|
||||
* On success: returns 0
|
||||
**/
|
||||
static void i40e_vsi_free_arrays(struct i40e_vsi *vsi)
|
||||
{
|
||||
/* free the ring and vector containers */
|
||||
kfree(vsi->q_vectors);
|
||||
vsi->q_vectors = NULL;
|
||||
kfree(vsi->tx_rings);
|
||||
vsi->tx_rings = NULL;
|
||||
vsi->rx_rings = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* i40e_vsi_clear - Deallocate the VSI provided
|
||||
* @vsi: the VSI being un-configured
|
||||
@ -5158,9 +5241,7 @@ static int i40e_vsi_clear(struct i40e_vsi *vsi)
|
||||
i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
|
||||
i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
|
||||
|
||||
/* free the ring and vector containers */
|
||||
kfree(vsi->q_vectors);
|
||||
kfree(vsi->tx_rings);
|
||||
i40e_vsi_free_arrays(vsi);
|
||||
|
||||
pf->vsi[vsi->idx] = NULL;
|
||||
if (vsi->idx < pf->next_vsi)
|
||||
@ -5183,7 +5264,7 @@ static s32 i40e_vsi_clear_rings(struct i40e_vsi *vsi)
|
||||
int i;
|
||||
|
||||
if (vsi->tx_rings[0])
|
||||
for (i = 0; i < vsi->alloc_queue_pairs; i++) {
|
||||
for (i = 0; i < vsi->num_queue_pairs; i++) {
|
||||
kfree_rcu(vsi->tx_rings[i], rcu);
|
||||
vsi->tx_rings[i] = NULL;
|
||||
vsi->rx_rings[i] = NULL;
|
||||
@ -5202,10 +5283,11 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)
|
||||
int i;
|
||||
|
||||
/* Set basic values in the rings to be used later during open() */
|
||||
for (i = 0; i < vsi->alloc_queue_pairs; i++) {
|
||||
for (i = 0; i < vsi->num_queue_pairs; i++) {
|
||||
struct i40e_ring *tx_ring;
|
||||
struct i40e_ring *rx_ring;
|
||||
|
||||
/* allocate space for both Tx and Rx in one shot */
|
||||
tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
|
||||
if (!tx_ring)
|
||||
goto err_out;
|
||||
@ -5533,15 +5615,34 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)
|
||||
**/
|
||||
static int i40e_config_rss(struct i40e_pf *pf)
|
||||
{
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
u32 lut = 0;
|
||||
int i, j;
|
||||
u64 hena;
|
||||
const u64 default_hena =
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD);
|
||||
|
||||
/* Set of random keys generated using kernel random number generator */
|
||||
static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
|
||||
0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
|
||||
0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
|
||||
0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
|
||||
struct i40e_hw *hw = &pf->hw;
|
||||
u32 lut = 0;
|
||||
int i, j;
|
||||
u64 hena;
|
||||
|
||||
/* Fill out hash function seed */
|
||||
for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
|
||||
@ -5550,16 +5651,7 @@ static int i40e_config_rss(struct i40e_pf *pf)
|
||||
/* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
|
||||
hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
|
||||
((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
|
||||
hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
|
||||
((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4)|
|
||||
((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);
|
||||
hena |= default_hena;
|
||||
wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
|
||||
wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
|
||||
|
||||
@ -5618,7 +5710,12 @@ static int i40e_sw_init(struct i40e_pf *pf)
|
||||
I40E_FLAG_MQ_ENABLED |
|
||||
I40E_FLAG_RX_1BUF_ENABLED;
|
||||
|
||||
/* Depending on PF configurations, it is possible that the RSS
|
||||
* maximum might end up larger than the available queues
|
||||
*/
|
||||
pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
|
||||
pf->rss_size_max = min_t(int, pf->rss_size_max,
|
||||
pf->hw.func_caps.num_tx_qp);
|
||||
if (pf->hw.func_caps.rss) {
|
||||
pf->flags |= I40E_FLAG_RSS_ENABLED;
|
||||
pf->rss_size = min_t(int, pf->rss_size_max,
|
||||
@ -5668,6 +5765,9 @@ static int i40e_sw_init(struct i40e_pf *pf)
|
||||
pf->num_req_vfs = min_t(int,
|
||||
pf->hw.func_caps.num_vfs,
|
||||
I40E_MAX_VF_COUNT);
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Number of VFs being requested for PF[%d] = %d\n",
|
||||
pf->hw.pf_id, pf->num_req_vfs);
|
||||
}
|
||||
#endif /* CONFIG_PCI_IOV */
|
||||
pf->eeprom_version = 0xDEAD;
|
||||
@ -5761,7 +5861,7 @@ static int i40e_config_netdev(struct i40e_vsi *vsi)
|
||||
int etherdev_size;
|
||||
|
||||
etherdev_size = sizeof(struct i40e_netdev_priv);
|
||||
netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
|
||||
netdev = alloc_etherdev_mq(etherdev_size, vsi->num_queue_pairs);
|
||||
if (!netdev)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -6525,11 +6625,13 @@ void i40e_veb_release(struct i40e_veb *veb)
|
||||
static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
|
||||
{
|
||||
bool is_default = (vsi->idx == vsi->back->lan_vsi);
|
||||
bool is_cloud = false;
|
||||
int ret;
|
||||
|
||||
/* get a VEB from the hardware */
|
||||
ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
|
||||
veb->enabled_tc, is_default, &veb->seid, NULL);
|
||||
veb->enabled_tc, is_default,
|
||||
is_cloud, &veb->seid, NULL);
|
||||
if (ret) {
|
||||
dev_info(&veb->pf->pdev->dev,
|
||||
"couldn't add VEB, err %d, aq_err %d\n",
|
||||
@ -6840,8 +6942,8 @@ static int i40e_setup_pf_switch(struct i40e_pf *pf)
|
||||
* into the pf, since this newer code pushes the pf queue
|
||||
* info down a level into a VSI
|
||||
*/
|
||||
pf->num_rx_queues = vsi->alloc_queue_pairs;
|
||||
pf->num_tx_queues = vsi->alloc_queue_pairs;
|
||||
pf->num_rx_queues = vsi->num_queue_pairs;
|
||||
pf->num_tx_queues = vsi->num_queue_pairs;
|
||||
} else {
|
||||
/* force a reset of TC and queue layout configurations */
|
||||
u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
|
||||
@ -7074,6 +7176,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
struct i40e_driver_version dv;
|
||||
struct i40e_pf *pf;
|
||||
struct i40e_hw *hw;
|
||||
static u16 pfs_found;
|
||||
int err = 0;
|
||||
u32 len;
|
||||
|
||||
@ -7139,6 +7242,18 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
hw->subsystem_device_id = pdev->subsystem_device;
|
||||
hw->bus.device = PCI_SLOT(pdev->devfn);
|
||||
hw->bus.func = PCI_FUNC(pdev->devfn);
|
||||
pf->instance = pfs_found;
|
||||
|
||||
/* do a special CORER for clearing PXE mode once at init */
|
||||
if (hw->revision_id == 0 &&
|
||||
(rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
|
||||
wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
|
||||
i40e_flush(hw);
|
||||
msleep(200);
|
||||
pf->corer_count++;
|
||||
|
||||
i40e_clear_pxe_mode(hw);
|
||||
}
|
||||
|
||||
/* Reset here to make sure all is clean and to define PF 'n' */
|
||||
err = i40e_pf_reset(hw);
|
||||
@ -7278,6 +7393,8 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
i40e_flush(hw);
|
||||
}
|
||||
|
||||
pfs_found++;
|
||||
|
||||
i40e_dbg_pf_init(pf);
|
||||
|
||||
/* tell the firmware that we're starting */
|
||||
|
||||
@ -106,7 +106,8 @@ i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
|
||||
u16 downlink_seid, u8 enabled_tc,
|
||||
bool default_port, u16 *pveb_seid,
|
||||
bool default_port, bool enable_l2_filtering,
|
||||
u16 *pveb_seid,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
|
||||
u16 veb_seid, u16 *switch_id, bool *floating,
|
||||
|
||||
@ -66,6 +66,7 @@
|
||||
#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880
|
||||
#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
|
||||
#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
|
||||
|
||||
#define I40E_PF_ARQBAH 0x00080180
|
||||
#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
|
||||
#define I40E_PF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_PF_ARQBAH_ARQBAH_SHIFT)
|
||||
@ -2187,6 +2188,12 @@
|
||||
#define I40E_GLPCI_PCIERR 0x000BE4FC
|
||||
#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
|
||||
#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
|
||||
#define I40E_GLPCI_PCITEST2 0x000BE4BC
|
||||
#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0
|
||||
#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK (0x1 << I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT)
|
||||
#define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT 1
|
||||
#define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK (0x1 << I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT)
|
||||
|
||||
#define I40E_GLPCI_PKTCT 0x0009C4BC
|
||||
#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
|
||||
#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
|
||||
|
||||
@ -891,13 +891,15 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
|
||||
static inline u32 i40e_rx_hash(struct i40e_ring *ring,
|
||||
union i40e_rx_desc *rx_desc)
|
||||
{
|
||||
if (ring->netdev->features & NETIF_F_RXHASH) {
|
||||
if ((le64_to_cpu(rx_desc->wb.qword1.status_error_len) >>
|
||||
I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
|
||||
I40E_RX_DESC_FLTSTAT_RSS_HASH)
|
||||
return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
|
||||
}
|
||||
return 0;
|
||||
const __le64 rss_mask =
|
||||
cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
|
||||
I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
|
||||
|
||||
if ((ring->netdev->features & NETIF_F_RXHASH) &&
|
||||
(rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
|
||||
return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -134,6 +134,7 @@ enum i40e_media_type {
|
||||
I40E_MEDIA_TYPE_BASET,
|
||||
I40E_MEDIA_TYPE_BACKPLANE,
|
||||
I40E_MEDIA_TYPE_CX4,
|
||||
I40E_MEDIA_TYPE_DA,
|
||||
I40E_MEDIA_TYPE_VIRTUAL
|
||||
};
|
||||
|
||||
@ -500,7 +501,8 @@ enum i40e_rx_desc_status_bits {
|
||||
I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
|
||||
I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
|
||||
I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
|
||||
I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 3 BITS */
|
||||
I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
|
||||
I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
|
||||
I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
|
||||
I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
|
||||
I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
|
||||
@ -509,9 +511,13 @@ enum i40e_rx_desc_status_bits {
|
||||
};
|
||||
|
||||
#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
|
||||
#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x7UL << \
|
||||
#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
|
||||
I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
|
||||
|
||||
#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
|
||||
#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
|
||||
I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
|
||||
|
||||
enum i40e_rx_desc_fltstat_values {
|
||||
I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
|
||||
I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user