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OMAPDSS: combine LCD related config into one func
Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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fb2cec1f72
@ -666,22 +666,8 @@ static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
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dispc_mgr_set_timings(mgr->id, &mp->timings);
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/* lcd_config parameters */
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if (dss_mgr_is_lcd(mgr->id)) {
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dispc_mgr_set_io_pad_mode(mp->lcd_config.io_pad_mode);
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dispc_mgr_enable_stallmode(mgr->id, mp->lcd_config.stallmode);
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dispc_mgr_enable_fifohandcheck(mgr->id,
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mp->lcd_config.fifohandcheck);
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dispc_mgr_set_clock_div(mgr->id, &mp->lcd_config.clock_info);
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dispc_mgr_set_tft_data_lines(mgr->id,
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mp->lcd_config.video_port_width);
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dispc_lcd_enable_signal_polarity(mp->lcd_config.lcden_sig_polarity);
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dispc_mgr_set_lcd_type_tft(mgr->id);
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}
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if (dss_mgr_is_lcd(mgr->id))
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dispc_mgr_set_lcd_config(mgr->id, &mp->lcd_config);
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mp->extra_info_dirty = false;
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if (mp->updating)
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@ -2768,7 +2768,7 @@ bool dispc_wb_is_enabled(void)
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return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
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}
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void dispc_lcd_enable_signal_polarity(bool act_high)
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static void dispc_lcd_enable_signal_polarity(bool act_high)
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{
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if (!dss_has_feature(FEAT_LCDENABLEPOL))
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return;
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@ -2792,13 +2792,13 @@ void dispc_pck_free_enable(bool enable)
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REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
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}
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void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
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static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
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{
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mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
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}
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void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
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static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
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{
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mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
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}
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@ -2854,7 +2854,7 @@ void dispc_mgr_setup(enum omap_channel channel,
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}
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}
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void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
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static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
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{
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int code;
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@ -2879,7 +2879,7 @@ void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
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mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
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}
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void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
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static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
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{
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u32 l;
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int gpout0, gpout1;
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@ -2908,11 +2908,28 @@ void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
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dispc_write_reg(DISPC_CONTROL, l);
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}
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void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
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static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
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{
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mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
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}
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void dispc_mgr_set_lcd_config(enum omap_channel channel,
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const struct dss_lcd_mgr_config *config)
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{
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dispc_mgr_set_io_pad_mode(config->io_pad_mode);
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dispc_mgr_enable_stallmode(channel, config->stallmode);
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dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
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dispc_mgr_set_clock_div(channel, &config->clock_info);
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dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
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dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
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dispc_mgr_set_lcd_type_tft(channel);
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}
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static bool _dispc_mgr_size_ok(u16 width, u16 height)
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{
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return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
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@ -409,7 +409,6 @@ void dispc_runtime_put(void);
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void dispc_enable_sidle(void);
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void dispc_disable_sidle(void);
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void dispc_lcd_enable_signal_polarity(bool act_high);
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void dispc_lcd_enable_signal(bool enable);
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void dispc_pck_free_enable(bool enable);
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void dispc_enable_fifomerge(bool enable);
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@ -436,7 +435,6 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable);
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void dispc_ovl_set_channel_out(enum omap_plane plane,
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enum omap_channel channel);
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void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
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u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
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u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
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bool dispc_mgr_go_busy(enum omap_channel channel);
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@ -444,10 +442,8 @@ void dispc_mgr_go(enum omap_channel channel);
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bool dispc_mgr_is_enabled(enum omap_channel channel);
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void dispc_mgr_enable(enum omap_channel channel, bool enable);
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bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
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void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
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void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
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void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
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void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
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void dispc_mgr_set_lcd_config(enum omap_channel channel,
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const struct dss_lcd_mgr_config *config);
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void dispc_mgr_set_timings(enum omap_channel channel,
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const struct omap_video_timings *timings);
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unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
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