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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[PATCH] forcedeth: TSO fix for large buffers
This contains a bug fix for large buffers. Originally, if a tx buffer to be sent was larger then the maximum size of the tx descriptor, it would overwrite other control bits. In this patch, the buffer is split over multiple descriptors. Also, the fragments are now setup in forward order. Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Manfred Spraul <manfred@colorfullife.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Ayaz Abdulla
Jeff Garzik
parent
3bb8a18ae8
commit
fa45459e5e
@ -101,6 +101,7 @@
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* 0.46: 20 Oct 2005: Add irq optimization modes.
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* 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
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* 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
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* 0.49: 10 Dec 2005: Fix tso for large buffers.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -112,7 +113,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.48"
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#define FORCEDETH_VERSION "0.49"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -349,6 +350,8 @@ typedef union _ring_type {
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#define NV_TX2_VALID (1<<31)
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#define NV_TX2_TSO (1<<28)
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#define NV_TX2_TSO_SHIFT 14
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#define NV_TX2_TSO_MAX_SHIFT 14
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#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
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#define NV_TX2_CHECKSUM_L3 (1<<27)
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#define NV_TX2_CHECKSUM_L4 (1<<26)
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@ -408,15 +411,15 @@ typedef union _ring_type {
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#define NV_WATCHDOG_TIMEO (5*HZ)
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#define RX_RING 128
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#define TX_RING 64
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#define TX_RING 256
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/*
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* If your nic mysteriously hangs then try to reduce the limits
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* to 1/0: It might be required to set NV_TX_LASTPACKET in the
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* last valid ring entry. But this would be impossible to
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* implement - probably a disassembly error.
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*/
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#define TX_LIMIT_STOP 63
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#define TX_LIMIT_START 62
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#define TX_LIMIT_STOP 255
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#define TX_LIMIT_START 254
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/* rx/tx mac addr + type + vlan + align + slack*/
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#define NV_RX_HEADERS (64)
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@ -535,6 +538,7 @@ struct fe_priv {
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unsigned int next_tx, nic_tx;
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struct sk_buff *tx_skbuff[TX_RING];
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dma_addr_t tx_dma[TX_RING];
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unsigned int tx_dma_len[TX_RING];
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u32 tx_flags;
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};
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@ -935,6 +939,7 @@ static void nv_init_tx(struct net_device *dev)
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else
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np->tx_ring.ex[i].FlagLen = 0;
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np->tx_skbuff[i] = NULL;
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np->tx_dma[i] = 0;
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}
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}
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@ -945,30 +950,27 @@ static int nv_init_ring(struct net_device *dev)
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return nv_alloc_rx(dev);
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}
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static void nv_release_txskb(struct net_device *dev, unsigned int skbnr)
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static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
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{
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struct fe_priv *np = netdev_priv(dev);
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struct sk_buff *skb = np->tx_skbuff[skbnr];
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unsigned int j, entry, fragments;
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dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n",
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dev->name, skbnr, np->tx_skbuff[skbnr]);
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entry = skbnr;
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if ((fragments = skb_shinfo(skb)->nr_frags) != 0) {
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for (j = fragments; j >= 1; j--) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1];
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pci_unmap_page(np->pci_dev, np->tx_dma[entry],
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frag->size,
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PCI_DMA_TODEVICE);
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entry = (entry - 1) % TX_RING;
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}
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dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
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dev->name, skbnr);
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if (np->tx_dma[skbnr]) {
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pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
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np->tx_dma_len[skbnr],
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PCI_DMA_TODEVICE);
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np->tx_dma[skbnr] = 0;
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}
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if (np->tx_skbuff[skbnr]) {
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dev_kfree_skb_irq(np->tx_skbuff[skbnr]);
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np->tx_skbuff[skbnr] = NULL;
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return 1;
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} else {
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return 0;
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}
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pci_unmap_single(np->pci_dev, np->tx_dma[entry],
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skb->len - skb->data_len,
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PCI_DMA_TODEVICE);
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dev_kfree_skb_irq(skb);
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np->tx_skbuff[skbnr] = NULL;
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}
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static void nv_drain_tx(struct net_device *dev)
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@ -981,10 +983,8 @@ static void nv_drain_tx(struct net_device *dev)
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np->tx_ring.orig[i].FlagLen = 0;
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else
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np->tx_ring.ex[i].FlagLen = 0;
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if (np->tx_skbuff[i]) {
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nv_release_txskb(dev, i);
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if (nv_release_txskb(dev, i))
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np->stats.tx_dropped++;
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}
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}
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}
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@ -1021,68 +1021,105 @@ static void drain_ring(struct net_device *dev)
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static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u32 tx_flags = 0;
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u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
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unsigned int fragments = skb_shinfo(skb)->nr_frags;
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unsigned int nr = (np->next_tx + fragments) % TX_RING;
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unsigned int nr = (np->next_tx - 1) % TX_RING;
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unsigned int start_nr = np->next_tx % TX_RING;
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unsigned int i;
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u32 offset = 0;
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u32 bcnt;
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u32 size = skb->len-skb->data_len;
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u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
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/* add fragments to entries count */
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for (i = 0; i < fragments; i++) {
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entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
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((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
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}
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spin_lock_irq(&np->lock);
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if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) {
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if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) {
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spin_unlock_irq(&np->lock);
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netif_stop_queue(dev);
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return NETDEV_TX_BUSY;
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}
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np->tx_skbuff[nr] = skb;
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if (fragments) {
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dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments);
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/* setup descriptors in reverse order */
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for (i = fragments; i >= 1; i--) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1];
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np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size,
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PCI_DMA_TODEVICE);
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/* setup the header buffer */
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do {
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bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
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nr = (nr + 1) % TX_RING;
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np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
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PCI_DMA_TODEVICE);
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np->tx_dma_len[nr] = bcnt;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
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np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
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} else {
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np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
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np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
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np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
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}
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tx_flags = np->tx_flags;
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offset += bcnt;
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size -= bcnt;
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} while(size);
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/* setup the fragments */
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for (i = 0; i < fragments; i++) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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u32 size = frag->size;
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offset = 0;
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do {
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bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
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nr = (nr + 1) % TX_RING;
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np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
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PCI_DMA_TODEVICE);
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np->tx_dma_len[nr] = bcnt;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
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np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
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np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
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} else {
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np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
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np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
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np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
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np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
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}
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nr = (nr - 1) % TX_RING;
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if (np->desc_ver == DESC_VER_1)
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tx_flags_extra &= ~NV_TX_LASTPACKET;
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else
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tx_flags_extra &= ~NV_TX2_LASTPACKET;
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}
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offset += bcnt;
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size -= bcnt;
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} while (size);
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}
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/* set last fragment flag */
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
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} else {
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np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
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}
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np->tx_skbuff[nr] = skb;
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#ifdef NETIF_F_TSO
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if (skb_shinfo(skb)->tso_size)
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tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
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tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
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else
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#endif
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tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
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tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
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np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len,
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PCI_DMA_TODEVICE);
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/* set tx flags */
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
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np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
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np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
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} else {
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np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
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np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
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np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
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np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
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}
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dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n",
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dev->name, np->next_tx, tx_flags_extra);
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dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
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dev->name, np->next_tx, entries, tx_flags_extra);
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{
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int j;
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for (j=0; j<64; j++) {
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@ -1093,7 +1130,7 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
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dprintk("\n");
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}
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np->next_tx += 1 + fragments;
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np->next_tx += entries;
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dev->trans_start = jiffies;
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spin_unlock_irq(&np->lock);
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@ -1140,7 +1177,6 @@ static void nv_tx_done(struct net_device *dev)
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np->stats.tx_packets++;
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np->stats.tx_bytes += skb->len;
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}
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nv_release_txskb(dev, i);
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}
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} else {
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if (Flags & NV_TX2_LASTPACKET) {
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@ -1156,9 +1192,9 @@ static void nv_tx_done(struct net_device *dev)
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np->stats.tx_packets++;
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np->stats.tx_bytes += skb->len;
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}
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nv_release_txskb(dev, i);
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}
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}
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nv_release_txskb(dev, i);
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np->nic_tx++;
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}
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if (np->next_tx - np->nic_tx < TX_LIMIT_START)
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@ -2456,7 +2492,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
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dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
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#ifdef NETIF_F_TSO
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/* disabled dev->features |= NETIF_F_TSO; */
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dev->features |= NETIF_F_TSO;
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#endif
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}
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