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ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds
The Kconfig options for the PL310 errata workarounds do not use a consistent naming scheme for either the config option or the bool description. This patch tidies up the options by ensuring that the bool descriptions are prefixed with "PL310 errata:" and the config options are prefixed with PL310_ERRATA_, making it much clearer in menuconfig as to what the workarounds are for. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231
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capabilities of the processor.
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config PL310_ERRATA_588369
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bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
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bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
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depends on CACHE_L2X0
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help
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The PL310 L2 cache controller implements three types of Clean &
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@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789
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entries regardless of the ASID.
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config PL310_ERRATA_727915
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bool "Background Clean & Invalidate by Way operation can cause data corruption"
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bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
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depends on CACHE_L2X0
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help
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PL310 implements the Clean & Invalidate by Way L2 cache maintenance
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@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472
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operation is received by a CPU before the ICIALLUIS has completed,
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potentially leading to corrupted entries in the cache or TLB.
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config ARM_ERRATA_753970
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bool "ARM errata: cache sync operation may be faulty"
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config PL310_ERRATA_753970
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bool "PL310 errata: cache sync operation may be faulty"
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depends on CACHE_PL310
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help
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This option enables the workaround for the 753970 PL310 (r3p0) erratum.
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@ -61,7 +61,7 @@ static inline void cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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#ifdef CONFIG_ARM_ERRATA_753970
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#ifdef CONFIG_PL310_ERRATA_753970
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/* write to an unmmapped register */
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writel_relaxed(0, base + L2X0_DUMMY_REG);
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#else
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