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Move OMAP Mailbox framework to drivers via Suman Anna <s-anna@ti.com>

Browse Source 
The OMAP Mailbox driver framework is moved out of arch/arm folder
 into drivers/mailbox folder, to re-enable building it and also serve
 as a baseline for adapting to the new mailbox driver framework. The
 changes mainly contain:
   - a minor bug fix and cleanup of mach-specific mailbox code
   - remove any header dependencies from plat-omap for multi-platform
     support
   - represent mailbox device data through platform data/hwmod attrs
   - move the omap mailbox code out of plat-omap/mach-omapX to
     drivers/mailbox folder
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJRvusIAAoJEBvUPslcq6VzQLoP/Rua4CwUWWYWOXGWW1/Mnf9m
 suVWrYDwkpcSmWeshNSthoF9d0iLKGTSK2mSNsqjBDyKwpqG3SHaS5vIPoRtc58T
 wHoS/a6rubo1ar8mWrxxHPP0eol0VXR1PwJGMNJrmx7Akzs6DHsiCgmTyoTTmSW7
 Rs9fJnfbV/DLz4nlmlL3sm+SDv7lbFZbowZPLKZl9LiUuoCIznq2hsIPW6XMufIa
 TeFpezMzxP55L2Yxya4Gc29bVSJO2PRdtn0d1UaJufcNfNdKnbrx0c2ksMwS8Kfn
 kuw3H5sohCN+vJX/Hd2OX0icv3W+k/6UtwBMZ3Nu65BvzAcggytskITCuGbRLOkz
 t0oKM5U+7tsnPpg5Wy/ZvuUj1TNgVrgbjWD26FnFbpRMnZ1kZGuIjgltrasGpjXP
 N7judIr1jgvy2+1sz8Rfeh0ymsu3PBss00A6hBk+WEErq554ajC4/e4p0Rk6GXPL
 SszQFdwOc/pvGTnbYR33BI1d465QEpgu6RDOevWKPGwmkqB0E7agQ/tOpp+M32Gu
 GL2YLFzqEr8cFZ6Rl/jixPXZnvjJs9GjzeQaSctgM1694kddwjWz3LnOUFUVlHFJ
 Vxg7ilw6YdrDvkdDxL2kiOQ3d9PAjaArhBjgPKgLr/riZ5+7XwY90eO70WvvhfJT
 S5Wklgl+mpILN/W6h6wy
 =j0vK
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v3.11/mailbox-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

From Tony Lindgren:

Move OMAP Mailbox framework to drivers via Suman Anna <s-anna@ti.com>

The OMAP Mailbox driver framework is moved out of arch/arm folder
into drivers/mailbox folder, to re-enable building it and also serve
as a baseline for adapting to the new mailbox driver framework. The
changes mainly contain:
  - a minor bug fix and cleanup of mach-specific mailbox code
  - remove any header dependencies from plat-omap for multi-platform
    support
  - represent mailbox device data through platform data/hwmod attrs
  - move the omap mailbox code out of plat-omap/mach-omapX to
    drivers/mailbox folder

* tag 'omap-for-v3.11/mailbox-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  mailbox/omap: move the OMAP mailbox framework to drivers
  ARM: OMAP2+: add user and fifo info to mailbox platform data
  ARM: OMAP2+: mbox: remove dependencies with soc.h
  omap: mailbox: correct the argument type for irq ops
  omap: mailbox: call request_irq after mbox queues are allocated
  omap: mailbox: check iomem resource before dereferencing it

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-20 21:41:06 +02:00
commit f9f697a77d
21 changed files with 360 additions and 281 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/configs/omap1_defconfig
View File

@ -26,7 +26,8 @@ CONFIG_ARCH_OMAP=y
CONFIG_ARCH_OMAP1=y
CONFIG_OMAP_RESET_CLOCKS=y
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_MBOX_FWK=y
CONFIG_MAILBOX=y
CONFIG_OMAP1_MBOX=y
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_DM_TIMER=y
CONFIG_ARCH_OMAP730=y

4
arch/arm/mach-omap1/Makefile
View File

@ -19,10 +19,6 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
# Power Management
obj-$(CONFIG_PM) += pm.o sleep.o
# DSP
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)

3
arch/arm/mach-omap2/Makefile
View File

@ -203,9 +203,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_OMAP3_EMU) += emu.o
obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
obj-y += $(iommu-m) $(iommu-y)

13
arch/arm/mach-omap2/devices.c
View File

@ -20,6 +20,7 @@
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/omap4-keypad.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/platform_data/mailbox-omap.h>
#include <linux/usb/omap_control_usb.h>
#include <asm/mach-types.h>
@ -327,25 +328,31 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
return 0;
}
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
static inline void __init omap_init_mbox(void)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
struct omap_mbox_pdata *pdata;
oh = omap_hwmod_lookup("mailbox");
if (!oh) {
pr_err("%s: unable to find hwmod\n", __func__);
return;
}
if (!oh->dev_attr) {
pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
return;
}
pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0);
pdata = (struct omap_mbox_pdata *)oh->dev_attr;
pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
__func__, PTR_ERR(pdev));
}
#else
static inline void omap_init_mbox(void) { }
#endif /* CONFIG_OMAP_MBOX_FWK */
#endif /* CONFIG_OMAP2PLUS_MBOX */
static inline void omap_init_sti(void) {}

14
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -16,6 +16,7 @@
#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"
@ -166,6 +167,18 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
};
/* mailbox */
static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
};
static struct omap_mbox_pdata omap2420_mailbox_attrs = {
.num_users = 4,
.num_fifos = 6,
.info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
.info = omap2420_mailbox_info,
};
static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
@ -186,6 +199,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap2420_mailbox_attrs,
};
/*

13
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -17,6 +17,7 @@
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"
@ -170,6 +171,17 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
};
/* mailbox */
static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
};
static struct omap_mbox_pdata omap2430_mailbox_attrs = {
.num_users = 4,
.num_fifos = 6,
.info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
.info = omap2430_mailbox_info,
};
static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
{ .irq = 26 + OMAP_INTC_START, },
{ .irq = -1 },
@ -189,6 +201,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap2430_mailbox_attrs,
};
/* mcspi3 */

13
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -25,6 +25,7 @@
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "am35xx.h"
@ -1505,6 +1506,17 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
.sysc = &omap3xxx_mailbox_sysc,
};
static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
};
static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
.num_users = 2,
.num_fifos = 2,
.info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
.info = omap3xxx_mailbox_info,
};
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
{ .irq = 26 + OMAP_INTC_START, },
{ .irq = -1 },
@ -1524,6 +1536,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap3xxx_mailbox_attrs,
};
/*

16
arch/arm/plat-omap/Kconfig
View File

@ -86,22 +86,6 @@ config OMAP_MUX_WARNINGS
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
config OMAP_MBOX_FWK
tristate "Mailbox framework support"
depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
help
Say Y here if you want to use OMAP Mailbox framework support for
DSP, IVA1.0 and IVA2 in OMAP1/2/3.
config OMAP_MBOX_KFIFO_SIZE
int "Mailbox kfifo default buffer size (bytes)"
depends on OMAP_MBOX_FWK
default 256
help
Specify the default size of mailbox's kfifo buffers (bytes).
This can also be changed at runtime (via the mbox_kfifo_size
module parameter).
config OMAP_IOMMU_IVA2
bool

3
arch/arm/plat-omap/Makefile
View File

@ -17,6 +17,3 @@ obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
# OMAP mailbox framework
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o

34
drivers/mailbox/Kconfig
View File

@ -16,4 +16,38 @@ config PL320_MBOX
Management Engine, primarily for cpufreq. Say Y here if you want
to use the PL320 IPCM support.
config OMAP_MBOX
tristate
help
This option is selected by any OMAP architecture specific mailbox
driver such as CONFIG_OMAP1_MBOX or CONFIG_OMAP2PLUS_MBOX. This
enables the common OMAP mailbox framework code.
config OMAP1_MBOX
tristate "OMAP1 Mailbox framework support"
depends on ARCH_OMAP1
select OMAP_MBOX
help
Mailbox implementation for OMAP chips with hardware for
interprocessor communication involving DSP in OMAP1. Say Y here
if you want to use OMAP1 Mailbox framework support.
config OMAP2PLUS_MBOX
tristate "OMAP2+ Mailbox framework support"
depends on ARCH_OMAP2PLUS
select OMAP_MBOX
help
Mailbox implementation for OMAP family chips with hardware for
interprocessor communication involving DSP, IVA1.0 and IVA2 in
OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
want to use OMAP2+ Mailbox framework support.
config OMAP_MBOX_KFIFO_SIZE
int "Mailbox kfifo default buffer size (bytes)"
depends on OMAP2PLUS_MBOX || OMAP1_MBOX
default 256
help
Specify the default size of mailbox's kfifo buffers (bytes).
This can also be changed at runtime (via the mbox_kfifo_size
module parameter).
endif

6
drivers/mailbox/Makefile
View File

@ -1 +1,7 @@
obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
obj-$(CONFIG_OMAP_MBOX) += omap-mailbox.o
obj-$(CONFIG_OMAP1_MBOX) += mailbox_omap1.o
mailbox_omap1-objs := mailbox-omap1.o
obj-$(CONFIG_OMAP2PLUS_MBOX) += mailbox_omap2.o
mailbox_omap2-objs := mailbox-omap2.o

12
arch/arm/mach-omap1/mailbox.c → drivers/mailbox/mailbox-omap1.c
View File

@ -13,7 +13,8 @@
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <plat/mailbox.h>
#include "omap-mbox.h"
#define MAILBOX_ARM2DSP1 0x00
#define MAILBOX_ARM2DSP1b 0x04
@ -86,21 +87,21 @@ static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
/* irq */
static void
omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
if (irq == IRQ_RX)
enable_irq(mbox->irq);
}
static void
omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
if (irq == IRQ_RX)
disable_irq(mbox->irq);
}
static int
omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
if (irq == IRQ_TX)
return 0;
@ -152,6 +153,9 @@ static int omap1_mbox_probe(struct platform_device *pdev)
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem)
return -ENOENT;
mbox_base = ioremap(mem->start, resource_size(mem));
if (!mbox_base)
return -ENOMEM;

286
arch/arm/mach-omap2/mailbox.c → drivers/mailbox/mailbox-omap2.c
View File

@ -11,15 +11,15 @@
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/mailbox.h>
#include "soc.h"
#include "omap-mbox.h"
#define MAILBOX_REVISION 0x000
#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
@ -59,11 +59,9 @@ struct omap_mbox2_priv {
u32 notfull_bit;
u32 ctx[OMAP4_MBOX_NR_REGS];
unsigned long irqdisable;
u32 intr_type;
};
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq);
static inline unsigned int mbox_read_reg(size_t ofs)
{
return __raw_readl(mbox_base + ofs);
@ -124,8 +122,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
}
/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
struct omap_mbox2_priv *p = mbox->priv;
u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
@ -135,20 +132,22 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
mbox_write_reg(l, p->irqenable);
}
static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
struct omap_mbox2_priv *p = mbox->priv;
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
if (!cpu_is_omap44xx())
/*
* Read and update the interrupt configuration register for pre-OMAP4.
* OMAP4 and later SoCs have a dedicated interrupt disabling register.
*/
if (!p->intr_type)
bit = mbox_read_reg(p->irqdisable) & ~bit;
mbox_write_reg(bit, p->irqdisable);
}
static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
struct omap_mbox2_priv *p = mbox->priv;
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
@ -159,8 +158,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
mbox_read_reg(p->irqstatus);
}
static int omap2_mbox_is_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
struct omap_mbox2_priv *p = mbox->priv;
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
@ -175,7 +173,8 @@ static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
int i;
struct omap_mbox2_priv *p = mbox->priv;
int nr_regs;
if (cpu_is_omap44xx())
if (p->intr_type)
nr_regs = OMAP4_MBOX_NR_REGS;
else
nr_regs = MBOX_NR_REGS;
@ -192,7 +191,8 @@ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
int i;
struct omap_mbox2_priv *p = mbox->priv;
int nr_regs;
if (cpu_is_omap44xx())
if (p->intr_type)
nr_regs = OMAP4_MBOX_NR_REGS;
else
nr_regs = MBOX_NR_REGS;
@ -220,192 +220,120 @@ static struct omap_mbox_ops omap2_mbox_ops = {
.restore_ctx = omap2_mbox_restore_ctx,
};
/*
* MAILBOX 0: ARM -> DSP,
* MAILBOX 1: ARM <- DSP.
* MAILBOX 2: ARM -> IVA,
* MAILBOX 3: ARM <- IVA.
*/
/* FIXME: the following structs should be filled automatically by the user id */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
.tx_fifo = {
.msg = MAILBOX_MESSAGE(0),
.fifo_stat = MAILBOX_FIFOSTATUS(0),
},
.rx_fifo = {
.msg = MAILBOX_MESSAGE(1),
.msg_stat = MAILBOX_MSGSTATUS(1),
},
.irqenable = MAILBOX_IRQENABLE(0),
.irqstatus = MAILBOX_IRQSTATUS(0),
.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
.irqdisable = MAILBOX_IRQENABLE(0),
};
struct omap_mbox mbox_dsp_info = {
.name = "dsp",
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_dsp_priv,
};
#endif
#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
#endif
#if defined(CONFIG_SOC_OMAP2420)
/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
.tx_fifo = {
.msg = MAILBOX_MESSAGE(2),
.fifo_stat = MAILBOX_FIFOSTATUS(2),
},
.rx_fifo = {
.msg = MAILBOX_MESSAGE(3),
.msg_stat = MAILBOX_MSGSTATUS(3),
},
.irqenable = MAILBOX_IRQENABLE(3),
.irqstatus = MAILBOX_IRQSTATUS(3),
.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
.irqdisable = MAILBOX_IRQENABLE(3),
};
static struct omap_mbox mbox_iva_info = {
.name = "iva",
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_iva_priv,
};
#endif
#ifdef CONFIG_ARCH_OMAP2
struct omap_mbox *omap2_mboxes[] = {
&mbox_dsp_info,
#ifdef CONFIG_SOC_OMAP2420
&mbox_iva_info,
#endif
NULL
};
#endif
#if defined(CONFIG_ARCH_OMAP4)
/* OMAP4 */
static struct omap_mbox2_priv omap2_mbox_1_priv = {
.tx_fifo = {
.msg = MAILBOX_MESSAGE(0),
.fifo_stat = MAILBOX_FIFOSTATUS(0),
},
.rx_fifo = {
.msg = MAILBOX_MESSAGE(1),
.msg_stat = MAILBOX_MSGSTATUS(1),
},
.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
};
struct omap_mbox mbox_1_info = {
.name = "mailbox-1",
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_1_priv,
};
static struct omap_mbox2_priv omap2_mbox_2_priv = {
.tx_fifo = {
.msg = MAILBOX_MESSAGE(3),
.fifo_stat = MAILBOX_FIFOSTATUS(3),
},
.rx_fifo = {
.msg = MAILBOX_MESSAGE(2),
.msg_stat = MAILBOX_MSGSTATUS(2),
},
.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
};
struct omap_mbox mbox_2_info = {
.name = "mailbox-2",
.ops = &omap2_mbox_ops,
.priv = &omap2_mbox_2_priv,
};
struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
#endif
static int omap2_mbox_probe(struct platform_device *pdev)
{
struct resource *mem;
int ret;
struct omap_mbox **list;
struct omap_mbox **list, *mbox, *mboxblk;
struct omap_mbox2_priv *priv, *privblk;
struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
struct omap_mbox_dev_info *info;
int i;
if (false)
;
#if defined(CONFIG_ARCH_OMAP3)
else if (cpu_is_omap34xx()) {
list = omap3_mboxes;
list[0]->irq = platform_get_irq(pdev, 0);
}
#endif
#if defined(CONFIG_ARCH_OMAP2)
else if (cpu_is_omap2430()) {
list = omap2_mboxes;
list[0]->irq = platform_get_irq(pdev, 0);
} else if (cpu_is_omap2420()) {
list = omap2_mboxes;
list[0]->irq = platform_get_irq_byname(pdev, "dsp");
list[1]->irq = platform_get_irq_byname(pdev, "iva");
}
#endif
#if defined(CONFIG_ARCH_OMAP4)
else if (cpu_is_omap44xx()) {
list = omap4_mboxes;
list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
}
#endif
else {
if (!pdata || !pdata->info_cnt || !pdata->info) {
pr_err("%s: platform not supported\n", __func__);
return -ENODEV;
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mbox_base = ioremap(mem->start, resource_size(mem));
if (!mbox_base)
/* allocate one extra for marking end of list */
list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL);
if (!list)
return -ENOMEM;
ret = omap_mbox_register(&pdev->dev, list);
if (ret) {
iounmap(mbox_base);
return ret;
mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL);
if (!mboxblk) {
ret = -ENOMEM;
goto free_list;
}
privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL);
if (!privblk) {
ret = -ENOMEM;
goto free_mboxblk;
}
info = pdata->info;
for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id);
priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
priv->rx_fifo.msg = MAILBOX_MESSAGE(info->rx_id);
priv->rx_fifo.msg_stat = MAILBOX_MSGSTATUS(info->rx_id);
priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
if (pdata->intr_type) {
priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id);
priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id);
priv->irqdisable =
OMAP4_MAILBOX_IRQENABLE_CLR(info->usr_id);
} else {
priv->irqenable = MAILBOX_IRQENABLE(info->usr_id);
priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id);
priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id);
}
priv->intr_type = pdata->intr_type;
mbox->priv = priv;
mbox->name = info->name;
mbox->ops = &omap2_mbox_ops;
mbox->irq = platform_get_irq(pdev, info->irq_id);
if (mbox->irq < 0) {
ret = mbox->irq;
goto free_privblk;
}
list[i] = mbox++;
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem) {
ret = -ENOENT;
goto free_privblk;
}
mbox_base = ioremap(mem->start, resource_size(mem));
if (!mbox_base) {
ret = -ENOMEM;
goto free_privblk;
}
ret = omap_mbox_register(&pdev->dev, list);
if (ret)
goto unmap_mbox;
platform_set_drvdata(pdev, list);
return 0;
unmap_mbox:
iounmap(mbox_base);
free_privblk:
kfree(privblk);
free_mboxblk:
kfree(mboxblk);
free_list:
kfree(list);
return ret;
}
static int omap2_mbox_remove(struct platform_device *pdev)
{
struct omap_mbox2_priv *privblk;
struct omap_mbox **list = platform_get_drvdata(pdev);
struct omap_mbox *mboxblk = list[0];
privblk = mboxblk->priv;
omap_mbox_unregister();
iounmap(mbox_base);
kfree(privblk);
kfree(mboxblk);
kfree(list);
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver omap2_mbox_driver = {
.probe = omap2_mbox_probe,
.remove = omap2_mbox_remove,
.driver = {
.probe = omap2_mbox_probe,
.remove = omap2_mbox_remove,
.driver = {
.name = "omap-mailbox",
},
};

54
arch/arm/plat-omap/mailbox.c → drivers/mailbox/omap-mailbox.c
View File

@ -31,7 +31,7 @@
#include <linux/notifier.h>
#include <linux/module.h>
#include <plat/mailbox.h>
#include "omap-mbox.h"
static struct omap_mbox **mboxes;
@ -116,6 +116,40 @@ int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
}
EXPORT_SYMBOL(omap_mbox_msg_send);
void omap_mbox_save_ctx(struct omap_mbox *mbox)
{
if (!mbox->ops->save_ctx) {
dev_err(mbox->dev, "%s:\tno save\n", __func__);
return;
}
mbox->ops->save_ctx(mbox);
}
EXPORT_SYMBOL(omap_mbox_save_ctx);
void omap_mbox_restore_ctx(struct omap_mbox *mbox)
{
if (!mbox->ops->restore_ctx) {
dev_err(mbox->dev, "%s:\tno restore\n", __func__);
return;
}
mbox->ops->restore_ctx(mbox);
}
EXPORT_SYMBOL(omap_mbox_restore_ctx);
void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
mbox->ops->enable_irq(mbox, irq);
}
EXPORT_SYMBOL(omap_mbox_enable_irq);
void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
mbox->ops->disable_irq(mbox, irq);
}
EXPORT_SYMBOL(omap_mbox_disable_irq);
static void mbox_tx_tasklet(unsigned long tx_data)
{
struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
@ -261,13 +295,6 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
}
if (!mbox->use_count++) {
ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
mbox->name, mbox);
if (unlikely(ret)) {
pr_err("failed to register mailbox interrupt:%d\n",
ret);
goto fail_request_irq;
}
mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
if (!mq) {
ret = -ENOMEM;
@ -282,17 +309,24 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
}
mbox->rxq = mq;
mq->mbox = mbox;
ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
mbox->name, mbox);
if (unlikely(ret)) {
pr_err("failed to register mailbox interrupt:%d\n",
ret);
goto fail_request_irq;
}
omap_mbox_enable_irq(mbox, IRQ_RX);
}
mutex_unlock(&mbox_configured_lock);
return 0;
fail_request_irq:
mbox_queue_free(mbox->rxq);
fail_alloc_rxq:
mbox_queue_free(mbox->txq);
fail_alloc_txq:
free_irq(mbox->irq, mbox);
fail_request_irq:
if (mbox->ops->shutdown)
mbox->ops->shutdown(mbox);
mbox->use_count--;

70
arch/arm/plat-omap/include/plat/mailbox.h → drivers/mailbox/omap-mbox.h
View File

@ -1,20 +1,20 @@
/* mailbox.h */
/*
* omap-mbox.h: OMAP mailbox internal definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MAILBOX_H
#define MAILBOX_H
#ifndef OMAP_MBOX_H
#define OMAP_MBOX_H
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/kfifo.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/kfifo.h>
typedef u32 mbox_msg_t;
struct omap_mbox;
typedef int __bitwise omap_mbox_irq_t;
#define IRQ_TX ((__force omap_mbox_irq_t) 1)
#define IRQ_RX ((__force omap_mbox_irq_t) 2)
#include <linux/omap-mailbox.h>
typedef int __bitwise omap_mbox_type_t;
#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
@ -51,55 +51,17 @@ struct omap_mbox_queue {
};
struct omap_mbox {
char *name;
const char *name;
unsigned int irq;
struct omap_mbox_queue *txq, *rxq;
struct omap_mbox_ops *ops;
struct device *dev;
void *priv;
int use_count;
struct blocking_notifier_head notifier;
struct blocking_notifier_head notifier;
};
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
void omap_mbox_init_seq(struct omap_mbox *);
struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
int omap_mbox_register(struct device *parent, struct omap_mbox **);
int omap_mbox_unregister(void);
static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
{
if (!mbox->ops->save_ctx) {
dev_err(mbox->dev, "%s:\tno save\n", __func__);
return;
}
mbox->ops->save_ctx(mbox);
}
static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
{
if (!mbox->ops->restore_ctx) {
dev_err(mbox->dev, "%s:\tno restore\n", __func__);
return;
}
mbox->ops->restore_ctx(mbox);
}
static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
omap_mbox_irq_t irq)
{
mbox->ops->enable_irq(mbox, irq);
}
static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
omap_mbox_irq_t irq)
{
mbox->ops->disable_irq(mbox, irq);
}
#endif /* MAILBOX_H */
#endif /* OMAP_MBOX_H */

3
drivers/remoteproc/Kconfig
View File

@ -14,8 +14,9 @@ config OMAP_REMOTEPROC
depends on HAS_DMA
depends on ARCH_OMAP4 || SOC_OMAP5
depends on OMAP_IOMMU
depends on OMAP_MBOX_FWK
select REMOTEPROC
select MAILBOX
select OMAP2PLUS_MBOX
select RPMSG
help
Say y here to support OMAP's remote processors (dual M3

2
drivers/remoteproc/omap_remoteproc.c
View File

@ -27,8 +27,8 @@
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/remoteproc.h>
#include <linux/omap-mailbox.h>
#include <plat/mailbox.h>
#include <linux/platform_data/remoteproc-omap.h>
#include "omap_remoteproc.h"

3
drivers/staging/tidspbridge/Kconfig
View File

@ -5,7 +5,8 @@
menuconfig TIDSPBRIDGE
tristate "DSP Bridge driver"
depends on ARCH_OMAP3 && !ARCH_MULTIPLATFORM
select OMAP_MBOX_FWK
select MAILBOX
select OMAP2PLUS_MBOX
help
DSP/BIOS Bridge is designed for platforms that contain a GPP and
one or more attached DSPs. The GPP is considered the master or

2
drivers/staging/tidspbridge/include/dspbridge/host_os.h
View File

@ -41,7 +41,7 @@
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <plat/mailbox.h>
#include <linux/omap-mailbox.h>
#include <linux/pagemap.h>
#include <asm/cacheflush.h>
#include <linux/dma-mapping.h>

29
include/linux/omap-mailbox.h Normal file
View File

@ -0,0 +1,29 @@
/*
* omap-mailbox: interprocessor communication module for OMAP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef OMAP_MAILBOX_H
#define OMAP_MAILBOX_H
typedef u32 mbox_msg_t;
struct omap_mbox;
typedef int __bitwise omap_mbox_irq_t;
#define IRQ_TX ((__force omap_mbox_irq_t) 1)
#define IRQ_RX ((__force omap_mbox_irq_t) 2)
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
void omap_mbox_save_ctx(struct omap_mbox *mbox);
void omap_mbox_restore_ctx(struct omap_mbox *mbox);
void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq);
void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq);
#endif /* OMAP_MAILBOX_H */

58
include/linux/platform_data/mailbox-omap.h Normal file
View File

@ -0,0 +1,58 @@
/*
* mailbox-omap.h
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _PLAT_MAILBOX_H
#define _PLAT_MAILBOX_H
/* Interrupt register configuration types */
#define MBOX_INTR_CFG_TYPE1 (0)
#define MBOX_INTR_CFG_TYPE2 (1)
/**
* struct omap_mbox_dev_info - OMAP mailbox device attribute info
* @name: name of the mailbox device
* @tx_id: mailbox queue id used for transmitting messages
* @rx_id: mailbox queue id on which messages are received
* @irq_id: irq identifier number to use from the hwmod data
* @usr_id: mailbox user id for identifying the interrupt into
* the MPU interrupt controller.
*/
struct omap_mbox_dev_info {
const char *name;
u32 tx_id;
u32 rx_id;
u32 irq_id;
u32 usr_id;
};
/**
* struct omap_mbox_pdata - OMAP mailbox platform data
* @intr_type: type of interrupt configuration registers used
while programming mailbox queue interrupts
* @num_users: number of users (processor devices) that the mailbox
* h/w block can interrupt
* @num_fifos: number of h/w fifos within the mailbox h/w block
* @info_cnt: number of mailbox devices for the platform
* @info: array of mailbox device attributes
*/
struct omap_mbox_pdata {
u32 intr_type;
u32 num_users;
u32 num_fifos;
u32 info_cnt;
struct omap_mbox_dev_info *info;
};
#endif /* _PLAT_MAILBOX_H */