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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 14:59:52 +07:00
ath10k: add copy engine register MAP for wcn3990 target
Copy engine is a host to target communication interface between wlan firmware and wlan wcn3990 platform driver. Add copy engine register map for wcn3990 wlan module. This add support for the copy engine source/destination ring configuration for wcn3990 chipset. Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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641fe28ad3
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f9e1830454
@ -2516,6 +2516,11 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
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ar->hw_ce_regs = &qcax_ce_regs;
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ar->hw_ce_regs = &qcax_ce_regs;
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ar->hw_values = &qca4019_values;
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ar->hw_values = &qca4019_values;
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break;
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break;
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case ATH10K_HW_WCN3990:
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ar->regs = &wcn3990_regs;
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ar->hw_ce_regs = &wcn3990_ce_regs;
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ar->hw_values = &wcn3990_values;
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break;
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default:
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default:
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ath10k_err(ar, "unsupported core hardware revision %d\n",
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ath10k_err(ar, "unsupported core hardware revision %d\n",
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hw_rev);
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hw_rev);
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@ -192,6 +192,156 @@ const struct ath10k_hw_values qca4019_values = {
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.ce_desc_meta_data_lsb = 4,
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.ce_desc_meta_data_lsb = 4,
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};
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};
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const struct ath10k_hw_regs wcn3990_regs = {
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.rtc_soc_base_address = 0x00000000,
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.rtc_wmac_base_address = 0x00000000,
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.soc_core_base_address = 0x00000000,
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.ce_wrapper_base_address = 0x0024C000,
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.ce0_base_address = 0x00240000,
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.ce1_base_address = 0x00241000,
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.ce2_base_address = 0x00242000,
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.ce3_base_address = 0x00243000,
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.ce4_base_address = 0x00244000,
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.ce5_base_address = 0x00245000,
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.ce6_base_address = 0x00246000,
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.ce7_base_address = 0x00247000,
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.ce8_base_address = 0x00248000,
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.ce9_base_address = 0x00249000,
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.ce10_base_address = 0x0024A000,
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.ce11_base_address = 0x0024B000,
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.soc_chip_id_address = 0x000000f0,
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.soc_reset_control_si0_rst_mask = 0x00000001,
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.soc_reset_control_ce_rst_mask = 0x00000100,
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.ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
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.ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
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.pcie_intr_fw_mask = 0x00100000,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
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.msb = 0x00000010,
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.lsb = 0x00000010,
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.mask = GENMASK(17, 17),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
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.msb = 0x00000012,
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.lsb = 0x00000012,
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.mask = GENMASK(18, 18),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
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.msb = 0x00000000,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
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.addr = 0x00000018,
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.src_ring = &wcn3990_src_ring,
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.dst_ring = &wcn3990_dst_ring,
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.dmax = &wcn3990_dmax,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
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.mask = GENMASK(0, 0),
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};
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static struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
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.copy_complete = &wcn3990_host_ie_cc,
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};
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static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
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.dstr_lmask = 0x00000010,
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.dstr_hmask = 0x00000008,
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.srcr_lmask = 0x00000004,
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.srcr_hmask = 0x00000002,
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.cc_mask = 0x00000001,
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.wm_mask = 0x0000001E,
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.addr = 0x00000030,
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};
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static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
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.axi_err = 0x00000100,
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.dstr_add_err = 0x00000200,
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.srcr_len_err = 0x00000100,
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.dstr_mlen_vio = 0x00000080,
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.dstr_overflow = 0x00000040,
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.srcr_overflow = 0x00000020,
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.err_mask = 0x000003E0,
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.addr = 0x00000038,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
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.msb = 0x00000000,
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.lsb = 0x00000010,
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.mask = GENMASK(31, 16),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
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.msb = 0x0000000f,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
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.addr = 0x0000004c,
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.low_rst = 0x00000000,
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.high_rst = 0x00000000,
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.wm_low = &wcn3990_src_wm_low,
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.wm_high = &wcn3990_src_wm_high,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
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.lsb = 0x00000010,
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.mask = GENMASK(31, 16),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
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.msb = 0x0000000f,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
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.addr = 0x00000050,
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.low_rst = 0x00000000,
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.high_rst = 0x00000000,
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.wm_low = &wcn3990_dst_wm_low,
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.wm_high = &wcn3990_dst_wm_high,
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};
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struct ath10k_hw_ce_regs wcn3990_ce_regs = {
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.sr_base_addr = 0x00000000,
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.sr_size_addr = 0x00000008,
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.dr_base_addr = 0x0000000c,
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.dr_size_addr = 0x00000014,
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.misc_ie_addr = 0x00000034,
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.sr_wr_index_addr = 0x0000003c,
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.dst_wr_index_addr = 0x00000040,
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.current_srri_addr = 0x00000044,
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.current_drri_addr = 0x00000048,
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.ddr_addr_for_rri_low = 0x00000004,
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.ddr_addr_for_rri_high = 0x00000008,
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.ce_rri_low = 0x0024C004,
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.ce_rri_high = 0x0024C008,
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.host_ie_addr = 0x0000002c,
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.ctrl1_regs = &wcn3990_ctrl1,
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.host_ie = &wcn3990_host_ie,
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.wm_regs = &wcn3990_wm_reg,
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.misc_regs = &wcn3990_misc_reg,
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.wm_srcr = &wcn3990_wm_src_ring,
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.wm_dstr = &wcn3990_wm_dst_ring,
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};
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const struct ath10k_hw_values wcn3990_values = {
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.rtc_state_val_on = 5,
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.ce_count = 12,
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.msi_assign_ce_max = 12,
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.num_target_ce_config_wlan = 12,
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.ce_desc_meta_data_mask = 0xFFF0,
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.ce_desc_meta_data_lsb = 4,
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
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static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
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.msb = 0x00000010,
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.msb = 0x00000010,
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.lsb = 0x00000010,
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.lsb = 0x00000010,
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@ -231,6 +231,7 @@ enum ath10k_hw_rev {
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ATH10K_HW_QCA9377,
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ATH10K_HW_QCA9377,
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ATH10K_HW_QCA4019,
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ATH10K_HW_QCA4019,
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ATH10K_HW_QCA9887,
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ATH10K_HW_QCA9887,
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ATH10K_HW_WCN3990,
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};
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};
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struct ath10k_hw_regs {
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struct ath10k_hw_regs {
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@ -247,6 +248,10 @@ struct ath10k_hw_regs {
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u32 ce5_base_address;
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u32 ce5_base_address;
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u32 ce6_base_address;
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u32 ce6_base_address;
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u32 ce7_base_address;
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u32 ce7_base_address;
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u32 ce8_base_address;
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u32 ce9_base_address;
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u32 ce10_base_address;
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u32 ce11_base_address;
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u32 soc_reset_control_si0_rst_mask;
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u32 soc_reset_control_si0_rst_mask;
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u32 soc_reset_control_ce_rst_mask;
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u32 soc_reset_control_ce_rst_mask;
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u32 soc_chip_id_address;
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u32 soc_chip_id_address;
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@ -267,6 +272,7 @@ extern const struct ath10k_hw_regs qca988x_regs;
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extern const struct ath10k_hw_regs qca6174_regs;
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extern const struct ath10k_hw_regs qca6174_regs;
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extern const struct ath10k_hw_regs qca99x0_regs;
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extern const struct ath10k_hw_regs qca99x0_regs;
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extern const struct ath10k_hw_regs qca4019_regs;
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extern const struct ath10k_hw_regs qca4019_regs;
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extern const struct ath10k_hw_regs wcn3990_regs;
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struct ath10k_hw_ce_regs_addr_map {
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struct ath10k_hw_ce_regs_addr_map {
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u32 msb;
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u32 msb;
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@ -362,6 +368,8 @@ extern const struct ath10k_hw_values qca6174_values;
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extern const struct ath10k_hw_values qca99x0_values;
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extern const struct ath10k_hw_values qca99x0_values;
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extern const struct ath10k_hw_values qca9888_values;
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extern const struct ath10k_hw_values qca9888_values;
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extern const struct ath10k_hw_values qca4019_values;
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extern const struct ath10k_hw_values qca4019_values;
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extern const struct ath10k_hw_values wcn3990_values;
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extern struct ath10k_hw_ce_regs wcn3990_ce_regs;
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extern struct ath10k_hw_ce_regs qcax_ce_regs;
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extern struct ath10k_hw_ce_regs qcax_ce_regs;
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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@ -375,6 +383,7 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
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#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
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#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
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#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
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#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
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#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
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#define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
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/* Known peculiarities:
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/* Known peculiarities:
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* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
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* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
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@ -1597,6 +1597,8 @@ void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
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* to mask irq/MSI.
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* to mask irq/MSI.
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*/
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*/
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break;
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break;
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case ATH10K_HW_WCN3990:
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break;
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}
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}
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}
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}
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@ -1623,6 +1625,8 @@ static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
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* to unmask irq/MSI.
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* to unmask irq/MSI.
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*/
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*/
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break;
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break;
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case ATH10K_HW_WCN3990:
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break;
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}
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}
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}
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}
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