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ARM: dts: omap5: add aes1 entry
OMAP5 has AES hardware cryptographic accelerator, add AES1 instance for it. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -247,6 +247,35 @@ emif2: emif@4d000000 {
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hw-caps-temp-alert;
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};
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aes1_target: target-module@4b501000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x4b501080 0x4>,
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<0x4b501084 0x4>,
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<0x4b501088 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
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clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4b501000 0x1000>;
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aes1: aes@0 {
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compatible = "ti,omap4-aes";
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reg = <0 0xa0>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 111>, <&sdma 110>;
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dma-names = "tx", "rx";
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};
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};
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bandgap: bandgap@4a0021e0 {
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reg = <0x4a0021e0 0xc
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0x4a00232c 0xc
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