AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-26 14:20:50 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk

Browse Source 
cpsw_cpts_rft_clk has got the choice of 3 clocksources
 -dpll_core_m4_ck
 -dpll_core_m5_ck
 -dpll_disp_m2_ck

By default dpll_core_m4_ck is selected, witn this as clock
source the CPTS doesnot work properly. It gives clockcheck errors
while running PTP.

 clockcheck: clock jumped backward or running slower than expected!

By selecting dpll_core_m5_ck as the clocksource fixes this issue.
In AM335x dpll_core_m5_ck is the default clocksource.

Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
George Cherian 2014-05-02 12:02:03 +05:30 committed by David S. Miller
parent 09c5537246
commit f9786f419d
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/clk/ti/clk-43xx.c
View File

@ -110,9 +110,25 @@ static struct ti_dt_clk am43xx_clks[] = {
int __init am43xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
ti_dt_clocks_register(am43xx_clks);
omap2_clk_disable_autoidle_all();
/*
* cpsw_cpts_rft_clk has got the choice of 3 clocksources
* dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
* By default dpll_core_m4_ck is selected, witn this as clock
* source the CPTS doesnot work properly. It gives clockcheck errors
* while running PTP.
* clockcheck: clock jumped backward or running slower than expected!
* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
* In AM335x dpll_core_m5_ck is the default clocksource.
*/
clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
clk_set_parent(clk1, clk2);
return 0;
}