mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 4.19, please pull the following: - Scott does a bunch of updates to the Stingray DTS and DTS include files to better support the addition of new boards. Scott also adds the Stingray OTP Device Tree node - Pramod updates the Stingray clocks such that they match the latest revision of the ASIC and datasheets - Ray sets the Stingray initial watchdog timeout to 60 seconds to give sufficient time for the kernel to boot and then adds PAXC (internal PCIe) support to the Stingray base DTS files - Vladimir adds support for the Stingray smart NIC PS225 boards variants -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJbSLiKAAoJEIfQlpxEBwcEDkYQAKXLAq/k5hZa3vRc86Hd0bqS 9tMBuqsL/o5rFP0gXgtjnZ8vOVpFtan8a16pldIlm13sS6bMUePTLF/ek7O+Ug+6 ScbTG/oKeZ9ztWnttSy5o20c2E1U2IN/ZwRSV1QPOOLsw+fDhUrv+sH3uEF2nbqK DVfQCoI+XhVauPDMVIJtM+4xor1YYPG4LCBvMUr9uqQX12XENd55IjHH8GSiTyvF +mUXPQtudceCnuZlYJDTnEJv3a9QwT2Jut+IFf25MNjQl/C2OiJZDCBsLJ8Di164 O5KnZ+NlZFjyxtgl5OTYDYw9n7AeitYyF8+fji7d2PqhD2/cRPOVEmpGpTXJva5R WSzfXmb4kGncAT48QlUfWZxjdLfC9SzZ0FO80rlAa1L5V8wEBYWzbEqder2/bLG3 DuwgfFzVX6Chvdb6U+Mky/DjWBWDv1BkqYJEUpgSf3vmHzVSFxHuNw4vj1p6Dmom lCzqdP8EuYBEKObrOkBs4/f/Uy7bwC4l8WMLrHXtXJj753LT/YsByS5W0h15A/2e 0q989PpcLoM5umijzi25DDJLLH1ZfjttsAydccDF500fSj+FhH6Q9YkVLClNOmyw 6o4Jxx/ukcEAB85UiQ9kg8v1iylgONhau2eFGMdnsHHYY9jWEsca28pDIMtPB5zS GvPZn9pS85230UJVbsLO =wh6F -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.19/devicetree-arm64' of https://github.com/Broadcom/stblinux into next/dt This pull request contains Broadcom ARM64-based SoCs Device Tree changes for 4.19, please pull the following: - Scott does a bunch of updates to the Stingray DTS and DTS include files to better support the addition of new boards. Scott also adds the Stingray OTP Device Tree node - Pramod updates the Stingray clocks such that they match the latest revision of the ASIC and datasheets - Ray sets the Stingray initial watchdog timeout to 60 seconds to give sufficient time for the kernel to boot and then adds PAXC (internal PCIe) support to the Stingray base DTS files - Vladimir adds support for the Stingray smart NIC PS225 boards variants * tag 'arm-soc/for-4.19/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: stingray: add bcm958802a802x dts arm64: dts: stingray: add PAXC support arm64: dts: set initial SR watchdog timeout to 60 seconds arm64: dts: Update Stingray clock DT nodes arm64: dts: stingray: Add OTP device node arm64: dts: stingray: move common board components to stingray-board-base Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
f9228c3836
@ -1,3 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb
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dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb
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dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958802a802x.dtb
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@ -30,20 +30,9 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "stingray.dtsi"
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#include "stingray-board-base.dtsi"
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &uart1;
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serial1 = &uart0;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
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compatible = "regulator-gpio";
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regulator-name = "sdio0_vddo_ctrl_reg";
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@ -67,11 +56,6 @@ sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
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};
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};
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&memory { /* Default DRAM banks */
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reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
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<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
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};
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&sata0 {
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status = "okay";
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};
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@ -136,18 +120,6 @@ &sata_phy7{
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status = "okay";
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};
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&mdio_mux_iproc {
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mdio@10 {
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gphy0: eth-phy@10 {
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reg = <0x10>;
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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&pwm {
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status = "okay";
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};
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@ -175,8 +147,6 @@ pcf8574: pcf8574@20 {
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};
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&enet {
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phy-mode = "rgmii-id";
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phy-handle = <&gphy0>;
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status = "okay";
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};
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@ -197,13 +167,10 @@ nandcs@0 {
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&sdio0 {
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vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
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non-removable;
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full-pwr-cycle;
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status = "okay";
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};
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&sdio1 {
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vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
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full-pwr-cycle;
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status = "okay";
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};
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26
arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts
Normal file
26
arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts
Normal file
@ -0,0 +1,26 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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*Copyright(c) 2018 Broadcom
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*/
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/dts-v1/;
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#include "stingray-board-base.dtsi"
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/ {
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compatible = "brcm,bcm958802a802x", "brcm,stingray";
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model = "Stingray PS225xx (BCM958802A802x)";
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};
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&enet {
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status = "disabled";
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};
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&sdio0 {
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no-1-8-v;
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright(c) 2016-2018 Broadcom
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*/
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#include "stingray.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart0;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&memory { /* Default DRAM banks */
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reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
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<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
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};
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&enet {
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phy-mode = "rgmii-id";
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phy-handle = <&gphy0>;
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};
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&uart1 {
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status = "okay";
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};
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&sdio0 {
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non-removable;
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full-pwr-cycle;
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};
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&sdio1 {
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full-pwr-cycle;
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};
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&mdio_mux_iproc {
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mdio@10 {
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gphy0: eth-phy@10 {
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reg = <0x10>;
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};
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};
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};
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@ -52,12 +52,24 @@ genpll0: genpll0@1d104 {
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reg = <0x0001d104 0x32>,
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<0x0001c854 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll0", "clk_125", "clk_scr",
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clock-output-names = "genpll0", "clk_125m", "clk_scr",
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"clk_250", "clk_pcie_axi",
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"clk_paxc_axi_x2",
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"clk_paxc_axi";
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};
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genpll2: genpll2@1d1ac {
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#clock-cells = <1>;
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compatible = "brcm,sr-genpll2";
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reg = <0x0001d1ac 0x32>,
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<0x0001c854 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll2", "clk_nic",
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"clk_ts_500_ref", "clk_125_nitro",
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"clk_chimp", "clk_nic_flash",
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"clk_fs";
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};
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genpll3: genpll3@1d1e0 {
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#clock-cells = <1>;
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compatible = "brcm,sr-genpll3";
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@ -75,8 +87,8 @@ genpll4: genpll4@1d214 {
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<0x0001c854 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll4", "clk_ccn",
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"clk_tpiu_pll", "noc_clk",
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"pll_chclk_fs4",
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"clk_tpiu_pll", "clk_noc",
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"clk_chclk_fs4",
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"clk_bridge_fscpu";
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};
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@ -86,8 +98,8 @@ genpll5: genpll5@1d248 {
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reg = <0x0001d248 0x32>,
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<0x0001c870 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll5", "fs4_hf_clk",
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"crypto_ae_clk", "raid_ae_clk";
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clock-output-names = "genpll5", "clk_fs4_hf",
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"clk_crypto_ae", "clk_raid_ae";
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};
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lcpll0: lcpll0@1d0c4 {
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@ -107,9 +119,9 @@ lcpll1: lcpll1@1d138 {
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reg = <0x0001d138 0x3c>,
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<0x0001c870 0x4>;
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clocks = <&osc>;
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clock-output-names = "lcpll1", "clk_wanpn",
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clock-output-names = "lcpll1", "clk_wan",
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"clk_usb_ref",
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"timesync_evt_clk";
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"clk_crmu_ts";
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};
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hsls_clk: hsls_clk {
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54
arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi
Normal file
54
arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi
Normal file
@ -0,0 +1,54 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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*Copyright(c) 2018 Broadcom
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*/
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pcie8: pcie@60400000 {
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compatible = "brcm,iproc-pcie-paxc-v2";
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reg = <0 0x60400000 0 0x1000>;
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linux,pci-domain = <8>;
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bus-range = <0x0 0x1>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
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dma-coherent;
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msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
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<0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
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<0x101 &gic_its 0x2080 0x1>, /* PF1 */
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<0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
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<0x102 &gic_its 0x2100 0x1>, /* PF2 */
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<0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
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<0x103 &gic_its 0x2180 0x1>, /* PF3 */
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<0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */
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<0x104 &gic_its 0x2200 0x1>, /* PF4 */
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<0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */
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<0x105 &gic_its 0x2280 0x1>, /* PF5 */
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<0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */
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<0x106 &gic_its 0x2300 0x1>, /* PF6 */
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<0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */
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<0x107 &gic_its 0x2380 0x1>, /* PF7 */
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<0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */
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phys = <&pcie_phy 8>;
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phy-names = "pcie-phy";
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};
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pcie-ss {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40000000 0x800>;
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pcie_phy: phy@0 {
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compatible = "brcm,sr-pcie-phy";
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reg = <0x0 0x200>;
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brcm,sr-cdru = <&cdru>;
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brcm,sr-mhb = <&mhb>;
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#phy-cells = <1>;
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};
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};
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@ -146,6 +146,11 @@ timer {
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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mhb: syscon@60401000 {
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compatible = "brcm,sr-mhb", "syscon";
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reg = <0 0x60401000 0 0x38c>;
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};
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scr {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -258,6 +263,18 @@ crmu: crmu {
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#include "stingray-clock.dtsi"
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otp: otp@1c400 {
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compatible = "brcm,ocotp-v2";
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reg = <0x0001c400 0x68>;
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brcm,ocotp-size = <2048>;
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status = "okay";
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};
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cdru: syscon@1d000 {
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compatible = "brcm,sr-cdru", "syscon";
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reg = <0x0001d000 0x400>;
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};
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gpio_crmu: gpio@24800 {
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compatible = "brcm,iproc-gpio";
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reg = <0x00024800 0x4c>;
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@ -269,6 +286,7 @@ gpio_crmu: gpio@24800 {
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#include "stingray-fs4.dtsi"
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#include "stingray-sata.dtsi"
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#include "stingray-pcie.dtsi"
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hsls {
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compatible = "simple-bus";
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@ -420,6 +438,7 @@ wdt0: watchdog@c0000 {
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
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clock-names = "wdogclk", "apb_pclk";
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timeout-sec = <60>;
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};
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gpio_hsls: gpio@d0000 {
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