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davinci: build list of unused EDMA events dynamically

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Currently, the edma_noevent list is passed from platform data.
But on some architectures, there will be many EDMA channels
which will not be used at all. This patch scans all the
platform devices and then builds a list of events which are
not being used. The unused event list will be used to allocate
EDMA channels in case of EDMA_CHANNEL_ANY usage instead of the
edma_noevent being used earlier for this purpose.

This patch is based on David Brownells's suggestion at
http://article.gmane.org/gmane.linux.davinci/15176.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sudhakar Rajashekhara 2010-01-06 17:29:49 +05:30 committed by Kevin Hilman
parent 447f18f1b4
commit f900d552f9
6 changed files with 43 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -83,11 +83,6 @@ struct platform_device da8xx_serial_device = {
},
};
static const s8 da8xx_dma_chan_no_event[] = {
20, 21,
-1
};
static const s8 da8xx_queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
@ -109,7 +104,6 @@ static struct edma_soc_info da8xx_edma_info[] = {
.n_slot = 128,
.n_tc = 2,
.n_cc = 1,
.noevent = da8xx_dma_chan_no_event,
.queue_tc_mapping = da8xx_queue_tc_mapping,
.queue_priority_mapping = da8xx_queue_priority_mapping,
},

8
arch/arm/mach-davinci/dm355.c
View File

@ -564,13 +564,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
static const s8 dma_chan_dm355_no_event[] = {
12, 13, 24, 56, 57,
58, 59, 60, 61, 62,
63,
-1
};
static const s8
queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
@ -594,7 +587,6 @@ static struct edma_soc_info dm355_edma_info[] = {
.n_slot = 128,
.n_tc = 2,
.n_cc = 1,
.noevent = dma_chan_dm355_no_event,
.queue_tc_mapping = queue_tc_mapping,
.queue_priority_mapping = queue_priority_mapping,
},

10
arch/arm/mach-davinci/dm644x.c
View File

@ -479,15 +479,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
static const s8 dma_chan_dm644x_no_event[] = {
0, 1, 12, 13, 14,
15, 25, 30, 31, 45,
46, 47, 55, 56, 57,
58, 59, 60, 61, 62,
63,
-1
};
static const s8
queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
@ -511,7 +502,6 @@ static struct edma_soc_info dm644x_edma_info[] = {
.n_slot = 128,
.n_tc = 2,
.n_cc = 1,
.noevent = dma_chan_dm644x_no_event,
.queue_tc_mapping = queue_tc_mapping,
.queue_priority_mapping = queue_priority_mapping,
},

9
arch/arm/mach-davinci/dm646x.c
View File

@ -511,14 +511,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
static const s8 dma_chan_dm646x_no_event[] = {
0, 1, 2, 3, 13,
14, 15, 24, 25, 26,
27, 30, 31, 54, 55,
56,
-1
};
/* Four Transfer Controllers on DM646x */
static const s8
dm646x_queue_tc_mapping[][2] = {
@ -547,7 +539,6 @@ static struct edma_soc_info dm646x_edma_info[] = {
.n_slot = 512,
.n_tc = 4,
.n_cc = 1,
.noevent = dma_chan_dm646x_no_event,
.queue_tc_mapping = dm646x_queue_tc_mapping,
.queue_priority_mapping = dm646x_queue_priority_mapping,
},

55
arch/arm/mach-davinci/dma.c
View File

@ -226,11 +226,11 @@ struct edma {
*/
DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
/* The edma_noevent bit for each channel is clear unless
* it doesn't trigger DMA events on this platform. It uses a
* bit of SOC-specific initialization code.
/* The edma_unused bit for each channel is clear unless
* it is not being used on this platform. It uses a bit
* of SOC-specific initialization code.
*/
DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
unsigned irq_res_start;
unsigned irq_res_end;
@ -556,8 +556,27 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
}
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
int i, ctlr;
for (i = 0; i < pdev->num_resources; i++) {
if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
(int)pdev->resource[i].start >= 0) {
ctlr = EDMA_CTLR(pdev->resource[i].start);
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
edma_info[ctlr]->edma_unused);
}
}
return 0;
}
/*-----------------------------------------------------------------------*/
static bool unused_chan_list_done;
/* Resource alloc/free: dma channels, parameter RAM slots */
/**
@ -596,6 +615,21 @@ int edma_alloc_channel(int channel,
enum dma_event_q eventq_no)
{
unsigned i, done = 0, ctlr = 0;
int ret = 0;
if (!unused_chan_list_done) {
/*
* Scan all the platform devices to find out the EDMA channels
* used and clear them in the unused list, making the rest
* available for ARM usage.
*/
ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
prepare_unused_channel_list);
if (ret < 0)
return ret;
unused_chan_list_done = true;
}
if (channel >= 0) {
ctlr = EDMA_CTLR(channel);
@ -607,7 +641,7 @@ int edma_alloc_channel(int channel,
channel = 0;
for (;;) {
channel = find_next_bit(edma_info[i]->
edma_noevent,
edma_unused,
edma_info[i]->num_channels,
channel);
if (channel == edma_info[i]->num_channels)
@ -1222,7 +1256,7 @@ int edma_start(unsigned channel)
unsigned int mask = (1 << (channel & 0x1f));
/* EDMA channels without event association */
if (test_bit(channel, edma_info[ctlr]->edma_noevent)) {
if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
pr_debug("EDMA: ESR%d %08x\n", j,
edma_shadow0_read_array(ctlr, SH_ESR, j));
edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@ -1347,7 +1381,6 @@ static int __init edma_probe(struct platform_device *pdev)
const s8 (*queue_tc_mapping)[2];
int i, j, found = 0;
int status = -1;
const s8 *noevent;
int irq[EDMA_MAX_CC] = {0, 0};
int err_irq[EDMA_MAX_CC] = {0, 0};
struct resource *r[EDMA_MAX_CC] = {NULL};
@ -1410,11 +1443,9 @@ static int __init edma_probe(struct platform_device *pdev)
memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
&dummy_paramset, PARM_SIZE);
noevent = info[j].noevent;
if (noevent) {
while (*noevent != -1)
set_bit(*noevent++, edma_info[j]->edma_noevent);
}
/* Mark all channels as unused */
memset(edma_info[j]->edma_unused, 0xff,
sizeof(edma_info[j]->edma_unused));
sprintf(irq_name, "edma%d", j);
irq[j] = platform_get_irq_byname(pdev, irq_name);

2
arch/arm/mach-davinci/include/mach/edma.h
View File

@ -280,8 +280,6 @@ struct edma_soc_info {
unsigned n_cc;
enum dma_event_q default_queue;
/* list of channels with no even trigger; terminated by "-1" */
const s8 *noevent;
const s8 (*queue_tc_mapping)[2];
const s8 (*queue_priority_mapping)[2];
};