mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 08:36:47 +07:00
Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Summary:
- Add UHD support on TM2/TM2E boards.
. adding interlace mode support and 297MHz pixel clock support
for UHD mode, setting sysreg register in case of HW trigger mode,
and adding SiI8620 MHL bridge device support.
- Fix trigger mode issue on Rinato board.
. On Rinato board, HW trigger mode doesn't work so fix it.
- Some fixup and cleanup.
* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
drm/exynos: fimd: Do not use HW trigger for exynos3250
drm/exynos/hdmi: add bridge support
drm/exynos/decon5433: signal vblank only on odd fields
drm/exynos/decon5433: add support for interlace modes
drm/exynos/hdmi: fix PLL for 27MHz settings
drm/exynos/hdmi: fix VSI infoframe registers
drm/exynos/hdmi: add 297MHz pixel clock support
drm/exynos: g2d: change platform driver name to 'exynos-drm-g2d'
drm/exynos/decon5433: configure sysreg in case of hardware trigger
This commit is contained in:
Dave Airlie
commit
f864b00e03
@ -13,9 +13,11 @@
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <video/exynos5433_decon.h>
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@ -25,6 +27,9 @@
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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#define DSD_CFG_MUX 0x1004
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#define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
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#define WINDOWS_NR 3
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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@ -57,6 +62,7 @@ struct decon_context {
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struct exynos_drm_plane planes[WINDOWS_NR];
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struct exynos_drm_plane_config configs[WINDOWS_NR];
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void __iomem *addr;
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struct regmap *sysreg;
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struct clk *clks[ARRAY_SIZE(decon_clks_name)];
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int pipe;
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unsigned long flags;
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@ -118,18 +124,29 @@ static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
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static void decon_setup_trigger(struct decon_context *ctx)
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{
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u32 val = !(ctx->out_type & I80_HW_TRG)
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? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
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TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
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: TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
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TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN;
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writel(val, ctx->addr + DECON_TRIGCON);
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if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
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return;
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if (!(ctx->out_type & I80_HW_TRG)) {
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writel(TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
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| TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
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ctx->addr + DECON_TRIGCON);
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return;
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}
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writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
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| TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
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if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
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DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
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DRM_ERROR("Cannot update sysreg.\n");
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}
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static void decon_commit(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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struct drm_display_mode *m = &crtc->base.mode;
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bool interlaced = false;
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u32 val;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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@ -140,13 +157,16 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
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m->crtc_hsync_end = m->crtc_htotal - 92;
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m->crtc_vsync_start = m->crtc_vdisplay + 1;
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m->crtc_vsync_end = m->crtc_vsync_start + 1;
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if (m->flags & DRM_MODE_FLAG_INTERLACE)
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interlaced = true;
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}
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if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG))
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decon_setup_trigger(ctx);
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decon_setup_trigger(ctx);
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/* lcd on and use command if */
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val = VIDOUT_LCD_ON;
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if (interlaced)
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val |= VIDOUT_INTERLACE_EN_F;
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if (ctx->out_type & IFTYPE_I80) {
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val |= VIDOUT_COMMAND_IF;
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} else {
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@ -155,15 +175,21 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
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writel(val, ctx->addr + DECON_VIDOUTCON0);
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val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
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VIDTCON2_HOZVAL(m->hdisplay - 1);
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if (interlaced)
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val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
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VIDTCON2_HOZVAL(m->hdisplay - 1);
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else
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val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
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VIDTCON2_HOZVAL(m->hdisplay - 1);
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writel(val, ctx->addr + DECON_VIDTCON2);
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if (!(ctx->out_type & IFTYPE_I80)) {
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val = VIDTCON00_VBPD_F(
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m->crtc_vtotal - m->crtc_vsync_end - 1) |
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VIDTCON00_VFPD_F(
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m->crtc_vsync_start - m->crtc_vdisplay - 1);
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int vbp = m->crtc_vtotal - m->crtc_vsync_end;
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int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
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if (interlaced)
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vbp = vbp / 2 - 1;
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val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
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writel(val, ctx->addr + DECON_VIDTCON00);
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val = VIDTCON01_VSPW_F(
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@ -278,12 +304,22 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
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writel(val, ctx->addr + DECON_VIDOSDxA(win));
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if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
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val = COORDINATE_X(state->crtc.x) |
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COORDINATE_Y(state->crtc.y / 2);
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writel(val, ctx->addr + DECON_VIDOSDxA(win));
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val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
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COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
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writel(val, ctx->addr + DECON_VIDOSDxB(win));
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val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
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COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
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writel(val, ctx->addr + DECON_VIDOSDxB(win));
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} else {
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val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
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writel(val, ctx->addr + DECON_VIDOSDxA(win));
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val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
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COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
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writel(val, ctx->addr + DECON_VIDOSDxB(win));
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}
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val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
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VIDOSD_Wx_ALPHA_B_F(0x0);
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@ -355,8 +391,6 @@ static void decon_swreset(struct decon_context *ctx)
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udelay(10);
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}
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WARN(tries == 0, "failed to disable DECON\n");
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writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
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for (tries = 2000; tries; --tries) {
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if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
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@ -557,6 +591,13 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id)
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if (val) {
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writel(val, ctx->addr + DECON_VIDINTCON1);
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if (ctx->out_type & IFTYPE_HDMI) {
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val = readl(ctx->addr + DECON_VIDOUTCON0);
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val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
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if (val ==
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(VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
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return IRQ_HANDLED;
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}
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drm_crtc_handle_vblank(&ctx->crtc->base);
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}
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@ -637,6 +678,15 @@ static int exynos5433_decon_probe(struct platform_device *pdev)
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ctx->out_type |= IFTYPE_I80;
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}
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if (ctx->out_type | I80_HW_TRG) {
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ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"samsung,disp-sysreg");
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if (IS_ERR(ctx->sysreg)) {
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dev_err(dev, "failed to get system register\n");
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return PTR_ERR(ctx->sysreg);
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}
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}
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for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
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struct clk *clk;
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@ -125,10 +125,8 @@ static struct fimd_driver_data exynos3_fimd_driver_data = {
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.timing_base = 0x20000,
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.lcdblk_offset = 0x210,
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.lcdblk_bypass_shift = 1,
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.trg_type = I80_HW_TRG,
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.has_shadowcon = 1,
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.has_vidoutcon = 1,
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.has_trigger_per_te = 1,
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};
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static struct fimd_driver_data exynos4_fimd_driver_data = {
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@ -1683,7 +1683,7 @@ struct platform_driver g2d_driver = {
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.probe = g2d_probe,
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.remove = g2d_remove,
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.driver = {
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.name = "s5p-g2d",
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.name = "exynos-drm-g2d",
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.owner = THIS_MODULE,
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.pm = &g2d_pm_ops,
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.of_match_table = exynos_g2d_match,
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@ -35,6 +35,7 @@
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/hdmi.h>
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#include <linux/component.h>
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#include <linux/mfd/syscon.h>
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@ -133,6 +134,7 @@ struct hdmi_context {
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struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
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struct regulator *reg_hdmi_en;
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struct exynos_drm_clk phy_clk;
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struct drm_bridge *bridge;
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};
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static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
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@ -509,9 +511,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
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{
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.pixel_clock = 27000000,
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.conf = {
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0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
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0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
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0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
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0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
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0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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@ -519,9 +521,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
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.pixel_clock = 27027000,
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.conf = {
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0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
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0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
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0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
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0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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@ -587,6 +589,15 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
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0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 297000000,
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.conf = {
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0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
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0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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};
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static const char * const hdmi_clk_gates4[] = {
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@ -788,7 +799,8 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata)
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sizeof(buf));
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if (ret > 0) {
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hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
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hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, ret);
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hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3);
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hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
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}
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ret = hdmi_audio_infoframe_init(&frm.audio);
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@ -912,7 +924,15 @@ static int hdmi_create_connector(struct drm_encoder *encoder)
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drm_connector_register(connector);
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drm_mode_connector_attach_encoder(connector, encoder);
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return 0;
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if (hdata->bridge) {
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encoder->bridge = hdata->bridge;
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hdata->bridge->encoder = encoder;
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ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
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if (ret)
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DRM_ERROR("Failed to attach bridge\n");
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}
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return ret;
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}
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static bool hdmi_mode_fixup(struct drm_encoder *encoder,
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@ -1581,6 +1601,31 @@ static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
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hdmiphy_disable(hdata);
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}
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static int hdmi_bridge_init(struct hdmi_context *hdata)
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{
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struct device *dev = hdata->dev;
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struct device_node *ep, *np;
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ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
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if (!ep)
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return 0;
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np = of_graph_get_remote_port_parent(ep);
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of_node_put(ep);
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if (!np) {
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DRM_ERROR("failed to get remote port parent");
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return -EINVAL;
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}
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hdata->bridge = of_drm_find_bridge(np);
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of_node_put(np);
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if (!hdata->bridge)
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return -EPROBE_DEFER;
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return 0;
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}
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static int hdmi_resources_init(struct hdmi_context *hdata)
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{
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struct device *dev = hdata->dev;
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@ -1620,17 +1665,18 @@ static int hdmi_resources_init(struct hdmi_context *hdata)
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hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
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if (PTR_ERR(hdata->reg_hdmi_en) == -ENODEV)
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return 0;
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if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {
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if (IS_ERR(hdata->reg_hdmi_en))
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return PTR_ERR(hdata->reg_hdmi_en);
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if (IS_ERR(hdata->reg_hdmi_en))
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return PTR_ERR(hdata->reg_hdmi_en);
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ret = regulator_enable(hdata->reg_hdmi_en);
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if (ret) {
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DRM_ERROR("failed to enable hdmi-en regulator\n");
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return ret;
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}
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}
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ret = regulator_enable(hdata->reg_hdmi_en);
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if (ret)
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DRM_ERROR("failed to enable hdmi-en regulator\n");
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return ret;
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return hdmi_bridge_init(hdata);
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}
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static struct of_device_id hdmi_match_types[] = {
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@ -89,6 +89,8 @@
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#define VIDCON0_ENVID_F (1 << 0)
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/* VIDOUTCON0 */
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#define VIDOUT_INTERLACE_FIELD_F (1 << 29)
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#define VIDOUT_INTERLACE_EN_F (1 << 28)
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#define VIDOUT_LCD_ON (1 << 24)
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#define VIDOUT_IF_F_MASK (0x3 << 20)
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#define VIDOUT_RGB_IF (0x0 << 20)
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