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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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wlcore/wl12xx: turn no-Tx-align quirk into Tx-align
Inverting the quirk flag to indicate Tx-alignment. This aligns it with the similar Rx-side quirk. The call to wl1271_set_block_size() decides whether SDIO block size alignment can be used or not. In case we're using SPI, we can't use the block size alignment, so the function returns false. So we set the quirk when wl1271_set_block_size() returns true and let the wl12xx lower driver unset the bit for wl127x (since it doesn't support this quirk). Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
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@ -272,9 +272,10 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
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wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
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wl->chip.id);
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wl->quirks |= WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT |
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WLCORE_QUIRK_LEGACY_NVS;
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wl->plt_fw_name = WL127X_PLT_FW_NAME;
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/* clear the alignment quirk, since we don't support it */
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wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
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wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
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wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
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wl->mr_fw_name = WL127X_FW_NAME_MULTI;
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@ -287,8 +288,10 @@ static int wl12xx_identify_chip(struct wl1271 *wl)
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wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
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wl->chip.id);
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wl->quirks |= WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT |
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WLCORE_QUIRK_LEGACY_NVS;
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/* clear the alignment quirk, since we don't support it */
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wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
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wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
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wl->plt_fw_name = WL127X_PLT_FW_NAME;
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wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
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wl->mr_fw_name = WL127X_FW_NAME_MULTI;
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@ -500,7 +500,7 @@ int wl1271_chip_specific_init(struct wl1271 *wl)
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if (wl->chip.id == CHIP_ID_1283_PG20) {
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u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
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if (!(wl->quirks & WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT))
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if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
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/* Enable SDIO padding */
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host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
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@ -1345,8 +1345,8 @@ static int wl12xx_chip_wakeup(struct wl1271 *wl, bool plt)
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* negligible, we use the same block size for all different
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* chip types.
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*/
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if (!wl1271_set_block_size(wl))
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wl->quirks |= WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT;
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if (wl1271_set_block_size(wl))
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wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
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ret = wl->ops->identify_chip(wl);
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if (ret < 0)
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@ -176,10 +176,10 @@ u8 wl12xx_tx_get_hlid(struct wl1271 *wl, struct wl12xx_vif *wlvif,
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unsigned int wlcore_calc_packet_alignment(struct wl1271 *wl,
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unsigned int packet_length)
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{
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if (wl->quirks & WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT)
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return ALIGN(packet_length, WL1271_TX_ALIGN_TO);
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else
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if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
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return ALIGN(packet_length, WL12XX_BUS_BLOCK_SIZE);
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else
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return ALIGN(packet_length, WL1271_TX_ALIGN_TO);
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}
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EXPORT_SYMBOL(wlcore_calc_packet_alignment);
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@ -353,7 +353,7 @@ int wlcore_free_hw(struct wl1271 *wl);
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#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
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/* wl127x and SPI don't support SDIO block size alignment */
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#define WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT BIT(2)
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#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
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/* means aggregated Rx packets are aligned to a SDIO block */
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#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
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