mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 02:26:41 +07:00
OMAP3: rework of the ASM sleep code execution paths
- Reworked and simplified the execution paths for better readability and to avoid duplication of code, - Added comments on the entry and exit points and the interaction with the ROM code for OFF mode restore, - Reworked the existing comments for better readability. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Jean Pihet
Kevin Hilman
parent
1e81bc015a
commit
f7dfe3d8a9
@ -239,7 +239,14 @@ void omap3_save_scratchpad_contents(void)
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struct omap3_scratchpad_prcm_block prcm_block_contents;
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struct omap3_scratchpad_sdrc_block sdrc_block_contents;
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/* Populate the Scratchpad contents */
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/*
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* Populate the Scratchpad contents
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*
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* The "get_*restore_pointer" functions are used to provide a
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* physical restore address where the ROM code jumps while waking
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* up from MPU OFF/OSWR state.
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* The restore pointer is stored into the scratchpad.
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*/
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scratchpad_contents.boot_config_ptr = 0x0;
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if (cpu_is_omap3630())
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scratchpad_contents.public_restore_ptr =
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@ -69,6 +69,13 @@
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/*
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* API functions
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*/
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/*
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* The "get_*restore_pointer" functions are used to provide a
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* physical restore address where the ROM code jumps while waking
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* up from MPU OFF/OSWR state.
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* The restore pointer is stored into the scratchpad.
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*/
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.text
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@ -102,7 +109,7 @@ ENTRY(get_es3_restore_pointer_sz)
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/*
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* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
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* This function sets up a flag that will allow for this toggling to take
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* place on 3630. Hopefully some version in the future maynot need this
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* place on 3630. Hopefully some version in the future may not need this.
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*/
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ENTRY(enable_omap3630_toggle_l2_on_restore)
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stmfd sp!, {lr} @ save registers on stack
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@ -143,35 +150,163 @@ api_params:
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ENTRY(save_secure_ram_context_sz)
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.word . - save_secure_ram_context
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/*
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* ======================
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* == Idle entry point ==
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* ======================
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*/
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/*
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* Forces OMAP into idle state
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*
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* omap34xx_suspend() - This bit of code just executes the WFI
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* for normal idles.
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* omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
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* and executes the WFI instruction. Calling WFI effectively changes the
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* power domains states to the desired target power states.
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*
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* Note: This code get's copied to internal SRAM at boot. When the OMAP
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* wakes up it continues execution at the point it went to sleep.
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*
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* Notes:
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* - this code gets copied to internal SRAM at boot. The execution pointer
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* in SRAM is _omap_sram_idle.
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* - when the OMAP wakes up it continues at different execution points
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* depending on the low power mode (non-OFF vs OFF modes),
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* cf. 'Resume path for xxx mode' comments.
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*/
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ENTRY(omap34xx_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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/* r0 contains restore pointer in sdram */
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/* r1 contains information about saving context */
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ldr r4, sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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orr r5, r5, #0x40 @ enable self refresh on idle req
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str r5, [r4] @ write back to SDRC_POWER register
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/*
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* r0 contains restore pointer in sdram
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* r1 contains information about saving context:
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* 0 - No context lost
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* 1 - Only L1 and logic lost
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* 2 - Only L2 lost
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* 3 - Both L1 and L2 lost
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*/
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/* Directly jump to WFI is the context save is not required */
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cmp r1, #0x0
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/* If context save is required, do that and execute wfi */
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bne save_context_wfi
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beq omap3_do_wfi
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/* Otherwise fall through to the save context code */
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save_context_wfi:
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mov r8, r0 @ Store SDRAM address in r8
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mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
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mov r4, #0x1 @ Number of parameters for restore call
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stmia r8!, {r4-r5} @ Push parameters for restore call
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mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
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stmia r8!, {r4-r5} @ Push parameters for restore call
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/* Check what that target sleep state is from r1 */
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cmp r1, #0x2 @ Only L2 lost, no need to save context
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beq clean_caches
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l1_logic_lost:
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/* Store sp and spsr to SDRAM */
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mov r4, sp
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mrs r5, spsr
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mov r6, lr
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stmia r8!, {r4-r6}
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/* Save all ARM registers */
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/* Coprocessor access control register */
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mrc p15, 0, r6, c1, c0, 2
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stmia r8!, {r6}
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/* TTBR0, TTBR1 and Translation table base control */
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mrc p15, 0, r4, c2, c0, 0
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mrc p15, 0, r5, c2, c0, 1
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mrc p15, 0, r6, c2, c0, 2
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stmia r8!, {r4-r6}
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/*
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* Domain access control register, data fault status register,
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* and instruction fault status register
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*/
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mrc p15, 0, r4, c3, c0, 0
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mrc p15, 0, r5, c5, c0, 0
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mrc p15, 0, r6, c5, c0, 1
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stmia r8!, {r4-r6}
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/*
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* Data aux fault status register, instruction aux fault status,
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* data fault address register and instruction fault address register
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*/
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mrc p15, 0, r4, c5, c1, 0
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mrc p15, 0, r5, c5, c1, 1
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mrc p15, 0, r6, c6, c0, 0
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mrc p15, 0, r7, c6, c0, 2
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stmia r8!, {r4-r7}
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/*
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* user r/w thread and process ID, user r/o thread and process ID,
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* priv only thread and process ID, cache size selection
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*/
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mrc p15, 0, r4, c13, c0, 2
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mrc p15, 0, r5, c13, c0, 3
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mrc p15, 0, r6, c13, c0, 4
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mrc p15, 2, r7, c0, c0, 0
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stmia r8!, {r4-r7}
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/* Data TLB lockdown, instruction TLB lockdown registers */
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mrc p15, 0, r5, c10, c0, 0
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mrc p15, 0, r6, c10, c0, 1
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stmia r8!, {r5-r6}
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/* Secure or non secure vector base address, FCSE PID, Context PID*/
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mrc p15, 0, r4, c12, c0, 0
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mrc p15, 0, r5, c13, c0, 0
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mrc p15, 0, r6, c13, c0, 1
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stmia r8!, {r4-r6}
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/* Primary remap, normal remap registers */
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mrc p15, 0, r4, c10, c2, 0
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mrc p15, 0, r5, c10, c2, 1
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stmia r8!,{r4-r5}
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/* Store current cpsr*/
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mrs r2, cpsr
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stmia r8!, {r2}
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mrc p15, 0, r4, c1, c0, 0
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/* save control register */
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stmia r8!, {r4}
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clean_caches:
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/*
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* Clean Data or unified cache to POU
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* How to invalidate only L1 cache???? - #FIX_ME#
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* mcr p15, 0, r11, c7, c11, 1
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*/
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cmp r1, #0x1 @ Check whether L2 inval is required
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beq omap3_do_wfi
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clean_l2:
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/*
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* jump out to kernel flush routine
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* - reuse that code is better
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* - it executes in a cached space so is faster than refetch per-block
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* - should be faster and will change with kernel
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* - 'might' have to copy address, load and jump to it
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*/
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ldr r1, kernel_flush
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mov lr, pc
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bx r1
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omap3_do_wfi:
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ldr r4, sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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orr r5, r5, #0x40 @ enable self refresh on idle req
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str r5, [r4] @ write back to SDRC_POWER register
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/* Data memory barrier and Data sync barrier */
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mov r1, #0
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mcr p15, 0, r1, c7, c10, 4
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mcr p15, 0, r1, c7, c10, 5
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/*
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* ===================================
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* == WFI instruction => Enter idle ==
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* ===================================
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*/
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wfi @ wait for interrupt
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/*
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* ===================================
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* == Resume path for non-OFF modes ==
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* ===================================
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*/
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nop
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nop
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nop
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@ -184,7 +319,29 @@ ENTRY(omap34xx_cpu_suspend)
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nop
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bl wait_sdrc_ok
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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/*
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* ===================================
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* == Exit point from non-OFF modes ==
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* ===================================
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*/
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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/*
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* ==============================
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* == Resume path for OFF mode ==
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* ==============================
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*/
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/*
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* The restore_* functions are called by the ROM code
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* when back from WFI in OFF mode.
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* Cf. the get_*restore_pointer functions.
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*
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* restore_es3: applies to 34xx >= ES3.0
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* restore_3630: applies to 36xx
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* restore: common code for 3xxx
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*/
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restore_es3:
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ldr r5, pm_prepwstst_core_p
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ldr r4, [r5]
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@ -214,12 +371,17 @@ restore_3630:
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ldr r1, control_mem_rta
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mov r2, #OMAP36XX_RTA_DISABLE
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str r2, [r1]
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/* Fall thru for the remaining logic */
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/* Fall through to common code for the remaining logic */
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restore:
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/* Check what was the reason for mpu reset and store the reason in r9*/
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/* 1 - Only L1 and logic lost */
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/* 2 - Only L2 lost - In this case, we wont be here */
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/* 3 - Both L1 and L2 lost */
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/*
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* Check what was the reason for mpu reset and store the reason in r9:
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* 0 - No context lost
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* 1 - Only L1 and logic lost
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* 2 - Only L2 lost - In this case, we wont be here
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* 3 - Both L1 and L2 lost
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*/
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ldr r1, pm_pwstctrl_mpu
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ldr r2, [r1]
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and r2, r2, #0x3
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@ -422,119 +584,12 @@ usettbr0:
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and r4, r2
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mcr p15, 0, r4, c1, c0, 0
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/*
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* ==============================
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* == Exit point from OFF mode ==
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* ==============================
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*/
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ldmfd sp!, {r0-r12, pc} @ restore regs and return
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save_context_wfi:
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mov r8, r0 /* Store SDRAM address in r8 */
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mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
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mov r4, #0x1 @ Number of parameters for restore call
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stmia r8!, {r4-r5} @ Push parameters for restore call
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mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
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stmia r8!, {r4-r5} @ Push parameters for restore call
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/* Check what that target sleep state is:stored in r1*/
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/* 1 - Only L1 and logic lost */
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/* 2 - Only L2 lost */
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/* 3 - Both L1 and L2 lost */
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cmp r1, #0x2 /* Only L2 lost */
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beq clean_l2
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cmp r1, #0x1 /* L2 retained */
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/* r9 stores whether to clean L2 or not*/
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moveq r9, #0x0 /* Dont Clean L2 */
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movne r9, #0x1 /* Clean L2 */
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l1_logic_lost:
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/* Store sp and spsr to SDRAM */
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mov r4, sp
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mrs r5, spsr
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mov r6, lr
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stmia r8!, {r4-r6}
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/* Save all ARM registers */
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/* Coprocessor access control register */
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mrc p15, 0, r6, c1, c0, 2
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stmia r8!, {r6}
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/* TTBR0, TTBR1 and Translation table base control */
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mrc p15, 0, r4, c2, c0, 0
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mrc p15, 0, r5, c2, c0, 1
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mrc p15, 0, r6, c2, c0, 2
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stmia r8!, {r4-r6}
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/* Domain access control register, data fault status register,
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and instruction fault status register */
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mrc p15, 0, r4, c3, c0, 0
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mrc p15, 0, r5, c5, c0, 0
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mrc p15, 0, r6, c5, c0, 1
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stmia r8!, {r4-r6}
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/* Data aux fault status register, instruction aux fault status,
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datat fault address register and instruction fault address register*/
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mrc p15, 0, r4, c5, c1, 0
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mrc p15, 0, r5, c5, c1, 1
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mrc p15, 0, r6, c6, c0, 0
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mrc p15, 0, r7, c6, c0, 2
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stmia r8!, {r4-r7}
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/* user r/w thread and process ID, user r/o thread and process ID,
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priv only thread and process ID, cache size selection */
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mrc p15, 0, r4, c13, c0, 2
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mrc p15, 0, r5, c13, c0, 3
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mrc p15, 0, r6, c13, c0, 4
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mrc p15, 2, r7, c0, c0, 0
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stmia r8!, {r4-r7}
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/* Data TLB lockdown, instruction TLB lockdown registers */
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mrc p15, 0, r5, c10, c0, 0
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mrc p15, 0, r6, c10, c0, 1
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stmia r8!, {r5-r6}
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/* Secure or non secure vector base address, FCSE PID, Context PID*/
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mrc p15, 0, r4, c12, c0, 0
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mrc p15, 0, r5, c13, c0, 0
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mrc p15, 0, r6, c13, c0, 1
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stmia r8!, {r4-r6}
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/* Primary remap, normal remap registers */
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mrc p15, 0, r4, c10, c2, 0
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mrc p15, 0, r5, c10, c2, 1
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stmia r8!,{r4-r5}
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/* Store current cpsr*/
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mrs r2, cpsr
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stmia r8!, {r2}
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mrc p15, 0, r4, c1, c0, 0
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/* save control register */
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stmia r8!, {r4}
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clean_caches:
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/* Clean Data or unified cache to POU*/
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/* How to invalidate only L1 cache???? - #FIX_ME# */
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/* mcr p15, 0, r11, c7, c11, 1 */
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cmp r9, #1 /* Check whether L2 inval is required or not*/
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bne skip_l2_inval
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clean_l2:
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/*
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* Jump out to kernel flush routine
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* - reuse that code is better
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* - it executes in a cached space so is faster than refetch per-block
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* - should be faster and will change with kernel
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* - 'might' have to copy address, load and jump to it
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* - lr is used since we are running in SRAM currently.
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*/
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ldr r1, kernel_flush
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mov lr, pc
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bx r1
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skip_l2_inval:
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/* Data memory barrier and Data sync barrier */
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mov r1, #0
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mcr p15, 0, r1, c7, c10, 4
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mcr p15, 0, r1, c7, c10, 5
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wfi @ wait for interrupt
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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bl wait_sdrc_ok
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/* restore regs and return */
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ldmfd sp!, {r0-r12, pc}
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/*
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@ -687,5 +742,6 @@ kick_counter:
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.word 0
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wait_dll_lock_counter:
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.word 0
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ENTRY(omap34xx_cpu_suspend_sz)
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.word . - omap34xx_cpu_suspend
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