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drm/i915/tgl: Add Wa_1409825376 to tgl

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Workaround database indicates we should disable VRH clockgating
in pre-production hardware.

V2:
 - Use REG_BIT macro
 - Update reference in commit message(Matt)

Bspec: 52890
Bspec: 49424
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200109223727.5630-1-radhakrishna.sripada@intel.com
This commit is contained in:
Radhakrishna Sripada 2020-01-09 14:37:27 -08:00 committed by Matt Roper
parent d54151c5c8
commit f78d5da6e7
2 changed files with 8 additions and 0 deletions
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3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4124,6 +4124,9 @@ enum {
#define PWM2_GATING_DIS (1 << 14) #define PWM2_GATING_DIS (1 << 14)
#define PWM1_GATING_DIS (1 << 13) #define PWM1_GATING_DIS (1 << 13)
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14) #define BXT_GMBUS_GATING_DIS (1 << 14)

5
drivers/gpu/drm/i915/intel_pm.c
View File

@ -6663,6 +6663,11 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(POWERGATE_ENABLE, I915_WRITE(POWERGATE_ENABLE,
I915_READ(POWERGATE_ENABLE) | vd_pg_enable); I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
/* Wa_1409825376:tgl (pre-prod)*/
if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
TGL_VRH_GATING_DIS);
} }
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)