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drm/amd/powerplay: guard manual mode prerequisite for clock level force

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Force clock level is for dpm manual mode only.

Reported-by: Candice Li <candice.li@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2019-08-30 17:30:46 +08:00 committed by Alex Deucher
parent 39857252e5
commit f78c47f669
3 changed files with 21 additions and 8 deletions
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18
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -1761,6 +1761,24 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
return ret; return ret;
} }
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
pr_debug("force clock level is for dpm manual mode only.\n");
return -EINVAL;
}
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
return ret;
}
const struct amd_ip_funcs smu_ip_funcs = { const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu", .name = "smu",
.early_init = smu_early_init, .early_init = smu_early_init,

5
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -635,8 +635,6 @@ struct smu_funcs
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0) ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
#define smu_print_clk_levels(smu, clk_type, buf) \ #define smu_print_clk_levels(smu, clk_type, buf) \
((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0) ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
#define smu_force_clk_levels(smu, clk_type, level) \
((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
#define smu_get_od_percentage(smu, type) \ #define smu_get_od_percentage(smu, type) \
((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0) ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
#define smu_set_od_percentage(smu, type, value) \ #define smu_set_od_percentage(smu, type, value) \
@ -834,5 +832,8 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature); const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf); size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
#endif #endif

6
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
View File

@ -1274,14 +1274,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
struct vega20_dpm_table *dpm_table; struct vega20_dpm_table *dpm_table;
struct vega20_single_dpm_table *single_dpm_table; struct vega20_single_dpm_table *single_dpm_table;
uint32_t soft_min_level, soft_max_level, hard_min_level; uint32_t soft_min_level, soft_max_level, hard_min_level;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
int ret = 0; int ret = 0;
if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
pr_info("force clock level is for dpm manual mode only.\n");
return -EINVAL;
}
mutex_lock(&(smu->mutex)); mutex_lock(&(smu->mutex));
soft_min_level = mask ? (ffs(mask) - 1) : 0; soft_min_level = mask ? (ffs(mask) - 1) : 0;