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drm/amd/powerplay: guard manual mode prerequisite for clock level force
Force clock level is for dpm manual mode only. Reported-by: Candice Li <candice.li@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1761,6 +1761,24 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
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return ret;
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}
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int smu_force_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t mask)
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{
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struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
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int ret = 0;
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if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
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pr_debug("force clock level is for dpm manual mode only.\n");
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return -EINVAL;
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}
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if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
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ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
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return ret;
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}
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const struct amd_ip_funcs smu_ip_funcs = {
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.name = "smu",
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.early_init = smu_early_init,
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@ -635,8 +635,6 @@ struct smu_funcs
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((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
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#define smu_print_clk_levels(smu, clk_type, buf) \
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((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
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#define smu_force_clk_levels(smu, clk_type, level) \
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((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
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#define smu_get_od_percentage(smu, type) \
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((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
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#define smu_set_od_percentage(smu, type, value) \
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@ -834,5 +832,8 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
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const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
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size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
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int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
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int smu_force_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t mask);
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#endif
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@ -1274,14 +1274,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
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struct vega20_dpm_table *dpm_table;
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struct vega20_single_dpm_table *single_dpm_table;
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uint32_t soft_min_level, soft_max_level, hard_min_level;
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struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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int ret = 0;
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if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
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pr_info("force clock level is for dpm manual mode only.\n");
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return -EINVAL;
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}
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mutex_lock(&(smu->mutex));
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soft_min_level = mask ? (ffs(mask) - 1) : 0;
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