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drm/nouveau: Use fallthrough pseudo-keyword

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Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
fall-through markings when it is the case.

[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through

Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Gustavo A. R. Silva 2020-07-07 12:36:28 -05:00 committed by Ben Skeggs
parent 7763d24f3b
commit f6e7393ede
17 changed files with 45 additions and 45 deletions
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2
drivers/gpu/drm/nouveau/dispnv50/disp.c
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@ -933,7 +933,7 @@ nv50_dp_bpc_to_depth(unsigned int bpc)
switch (bpc) { switch (bpc) {
case 6: return 0x2; case 6: return 0x2;
case 8: return 0x5; case 8: return 0x5;
case 10: /* fall-through */ case 10:
default: return 0x6; default: return 0x6;
} }
} }

2
drivers/gpu/drm/nouveau/nouveau_bo.c
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@ -1461,7 +1461,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
/* untiled */ /* untiled */
break; break;
/* fall through - tiled memory */ fallthrough; /* tiled memory */
case TTM_PL_VRAM: case TTM_PL_VRAM:
reg->bus.offset = reg->start << PAGE_SHIFT; reg->bus.offset = reg->start << PAGE_SHIFT;
reg->bus.base = device->func->resource_addr(device, 1); reg->bus.base = device->func->resource_addr(device, 1);

4
drivers/gpu/drm/nouveau/nouveau_connector.c
View File

@ -330,7 +330,7 @@ nouveau_conn_attach_properties(struct drm_connector *connector)
case DRM_MODE_CONNECTOR_VGA: case DRM_MODE_CONNECTOR_VGA:
if (disp->disp.object.oclass < NV50_DISP) if (disp->disp.object.oclass < NV50_DISP)
break; /* Can only scale on DFPs. */ break; /* Can only scale on DFPs. */
/* Fall-through. */ fallthrough;
default: default:
drm_object_attach_property(&connector->base, dev->mode_config. drm_object_attach_property(&connector->base, dev->mode_config.
scaling_mode_property, scaling_mode_property,
@ -445,7 +445,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector)
case DCB_OUTPUT_LVDS: case DCB_OUTPUT_LVDS:
switcheroo_ddc = !!(vga_switcheroo_handler_flags() & switcheroo_ddc = !!(vga_switcheroo_handler_flags() &
VGA_SWITCHEROO_CAN_SWITCH_DDC); VGA_SWITCHEROO_CAN_SWITCH_DDC);
/* fall-through */ fallthrough;
default: default:
if (!nv_encoder->i2c) if (!nv_encoder->i2c)
break; break;

34
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c
View File

@ -23,55 +23,55 @@ void pack_hdmi_infoframe(struct packed_hdmi_infoframe *packed_frame,
*/ */
case 17: case 17:
subpack1_high = (raw_frame[16] << 16); subpack1_high = (raw_frame[16] << 16);
/* fall through */ fallthrough;
case 16: case 16:
subpack1_high |= (raw_frame[15] << 8); subpack1_high |= (raw_frame[15] << 8);
/* fall through */ fallthrough;
case 15: case 15:
subpack1_high |= raw_frame[14]; subpack1_high |= raw_frame[14];
/* fall through */ fallthrough;
case 14: case 14:
subpack1_low = (raw_frame[13] << 24); subpack1_low = (raw_frame[13] << 24);
/* fall through */ fallthrough;
case 13: case 13:
subpack1_low |= (raw_frame[12] << 16); subpack1_low |= (raw_frame[12] << 16);
/* fall through */ fallthrough;
case 12: case 12:
subpack1_low |= (raw_frame[11] << 8); subpack1_low |= (raw_frame[11] << 8);
/* fall through */ fallthrough;
case 11: case 11:
subpack1_low |= raw_frame[10]; subpack1_low |= raw_frame[10];
/* fall through */ fallthrough;
case 10: case 10:
subpack0_high = (raw_frame[9] << 16); subpack0_high = (raw_frame[9] << 16);
/* fall through */ fallthrough;
case 9: case 9:
subpack0_high |= (raw_frame[8] << 8); subpack0_high |= (raw_frame[8] << 8);
/* fall through */ fallthrough;
case 8: case 8:
subpack0_high |= raw_frame[7]; subpack0_high |= raw_frame[7];
/* fall through */ fallthrough;
case 7: case 7:
subpack0_low = (raw_frame[6] << 24); subpack0_low = (raw_frame[6] << 24);
/* fall through */ fallthrough;
case 6: case 6:
subpack0_low |= (raw_frame[5] << 16); subpack0_low |= (raw_frame[5] << 16);
/* fall through */ fallthrough;
case 5: case 5:
subpack0_low |= (raw_frame[4] << 8); subpack0_low |= (raw_frame[4] << 8);
/* fall through */ fallthrough;
case 4: case 4:
subpack0_low |= raw_frame[3]; subpack0_low |= raw_frame[3];
/* fall through */ fallthrough;
case 3: case 3:
header = (raw_frame[2] << 16); header = (raw_frame[2] << 16);
/* fall through */ fallthrough;
case 2: case 2:
header |= (raw_frame[1] << 8); header |= (raw_frame[1] << 8);
/* fall through */ fallthrough;
case 1: case 1:
header |= raw_frame[0]; header |= raw_frame[0];
/* fall through */ fallthrough;
case 0: case 0:
break; break;
} }

2
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
View File

@ -122,7 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
break; break;
case NV_MEM_ACCESS_WO: case NV_MEM_ACCESS_WO:
dmaobj->flags0 |= 0x00008000; dmaobj->flags0 |= 0x00008000;
/* fall through */ fallthrough;
case NV_MEM_ACCESS_RW: case NV_MEM_ACCESS_RW:
dmaobj->flags2 |= 0x00000002; dmaobj->flags2 |= 0x00000002;
break; break;

4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
View File

@ -117,10 +117,10 @@ nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data)
switch (mthd) { switch (mthd) {
case 0x0000 ... 0x0000: /* subchannel's engine -> software */ case 0x0000 ... 0x0000: /* subchannel's engine -> software */
nvkm_wr32(device, 0x003280, (engine &= ~mask)); nvkm_wr32(device, 0x003280, (engine &= ~mask));
/* fall through */ fallthrough;
case 0x0180 ... 0x01fc: /* handle -> instance */ case 0x0180 ... 0x01fc: /* handle -> instance */
data = nvkm_rd32(device, 0x003258) & 0x0000ffff; data = nvkm_rd32(device, 0x003258) & 0x0000ffff;
/* fall through */ fallthrough;
case 0x0100 ... 0x017c: case 0x0100 ... 0x017c:
case 0x0200 ... 0x1ffc: /* pass method down to sw */ case 0x0200 ... 0x1ffc: /* pass method down to sw */
if (!(engine & mask) && sw) if (!(engine & mask) && sw)

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View File

@ -81,7 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base)
case 0x49: case 0x49:
case 0x4b: case 0x4b:
nvkm_wr32(device, 0x002230, 0x00000001); nvkm_wr32(device, 0x002230, 0x00000001);
/* fall through */ fallthrough;
case 0x40: case 0x40:
case 0x41: case 0x41:
case 0x42: case 0x42:

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
View File

@ -172,8 +172,8 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len,
outp->dpconf.link_nr = 1; outp->dpconf.link_nr = 1;
break; break;
} }
fallthrough;
/* fall-through... */
case DCB_OUTPUT_TMDS: case DCB_OUTPUT_TMDS:
case DCB_OUTPUT_LVDS: case DCB_OUTPUT_LVDS:
outp->link = (conf & 0x00000030) >> 4; outp->link = (conf & 0x00000030) >> 4;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c
View File

@ -100,7 +100,7 @@ nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx,
switch (*ver) { switch (*ver) {
case 0x20: case 0x20:
info->mask |= 0x00c0; /* match any link */ info->mask |= 0x00c0; /* match any link */
/* fall-through */ fallthrough;
case 0x21: case 0x21:
case 0x30: case 0x30:
info->flags = nvbios_rd08(bios, data + 0x05); info->flags = nvbios_rd08(bios, data + 0x05);

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
View File

@ -135,7 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx,
break; break;
case 0x30: case 0x30:
info->script = nvbios_rd16(bios, perf + 0x02); info->script = nvbios_rd16(bios, perf + 0x02);
/* fall through */ fallthrough;
case 0x35: case 0x35:
info->fanspeed = nvbios_rd08(bios, perf + 0x06); info->fanspeed = nvbios_rd08(bios, perf + 0x06);
info->voltage = nvbios_rd08(bios, perf + 0x07); info->voltage = nvbios_rd08(bios, perf + 0x07);

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
View File

@ -134,7 +134,7 @@ pll_map(struct nvkm_bios *bios)
device->chipset == 0xaa || device->chipset == 0xaa ||
device->chipset == 0xac) device->chipset == 0xac)
return g84_pll_mapping; return g84_pll_mapping;
/* fall through */ fallthrough;
default: default:
return NULL; return NULL;
} }

10
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
View File

@ -115,21 +115,21 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
switch (min_t(u8, *hdr, 25)) { switch (min_t(u8, *hdr, 25)) {
case 25: case 25:
p->timing_10_24 = nvbios_rd08(bios, data + 0x18); p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
/* fall through */ fallthrough;
case 24: case 24:
case 23: case 23:
case 22: case 22:
p->timing_10_21 = nvbios_rd08(bios, data + 0x15); p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
/* fall through */ fallthrough;
case 21: case 21:
p->timing_10_20 = nvbios_rd08(bios, data + 0x14); p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
/* fall through */ fallthrough;
case 20: case 20:
p->timing_10_CWL = nvbios_rd08(bios, data + 0x13); p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
/* fall through */ fallthrough;
case 19: case 19:
p->timing_10_18 = nvbios_rd08(bios, data + 0x12); p->timing_10_18 = nvbios_rd08(bios, data + 0x12);
/* fall through */ fallthrough;
case 18: case 18:
case 17: case 17:
p->timing_10_16 = nvbios_rd08(bios, data + 0x10); p->timing_10_16 = nvbios_rd08(bios, data + 0x10);

2
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View File

@ -90,7 +90,7 @@ nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate,
case NVKM_CLK_BOOST_NONE: case NVKM_CLK_BOOST_NONE:
if (clk->base_khz && freq > clk->base_khz) if (clk->base_khz && freq > clk->base_khz)
return false; return false;
/* fall through */ fallthrough;
case NVKM_CLK_BOOST_BIOS: case NVKM_CLK_BOOST_BIOS:
if (clk->boost_khz && freq > clk->boost_khz) if (clk->boost_khz && freq > clk->boost_khz)
return false; return false;

2
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
View File

@ -363,7 +363,7 @@ mcp77_clk_prog(struct nvkm_clk *base)
switch (clk->vsrc) { switch (clk->vsrc) {
case nv_clk_src_cclk: case nv_clk_src_cclk:
mast |= 0x00400000; mast |= 0x00400000;
/* fall through */ fallthrough;
default: default:
nvkm_wr32(device, 0x4600, clk->vdiv); nvkm_wr32(device, 0x4600, clk->vdiv);
} }

12
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
View File

@ -119,11 +119,11 @@ powerctrl_1_shift(int chip_version, int reg)
switch (reg) { switch (reg) {
case 0x680520: case 0x680520:
shift += 4; /* fall through */ shift += 4; fallthrough;
case 0x680508: case 0x680508:
shift += 4; /* fall through */ shift += 4; fallthrough;
case 0x680504: case 0x680504:
shift += 4; /* fall through */ shift += 4; fallthrough;
case 0x680500: case 0x680500:
shift += 4; shift += 4;
} }
@ -245,11 +245,11 @@ setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1,
switch (reg1) { switch (reg1) {
case 0x680504: case 0x680504:
shift_c040 += 2; /* fall through */ shift_c040 += 2; fallthrough;
case 0x680500: case 0x680500:
shift_c040 += 2; /* fall through */ shift_c040 += 2; fallthrough;
case 0x680520: case 0x680520:
shift_c040 += 2; /* fall through */ shift_c040 += 2; fallthrough;
case 0x680508: case 0x680508:
shift_c040 += 2; shift_c040 += 2;
} }

4
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
View File

@ -131,13 +131,13 @@ nv40_ram_prog(struct nvkm_ram *base)
nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl);
nvkm_wr32(device, 0x004048, ram->coef); nvkm_wr32(device, 0x004048, ram->coef);
nvkm_wr32(device, 0x004030, ram->coef); nvkm_wr32(device, 0x004030, ram->coef);
/* fall through */ fallthrough;
case 0x43: case 0x43:
case 0x49: case 0x49:
case 0x4b: case 0x4b:
nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl);
nvkm_wr32(device, 0x00403c, ram->coef); nvkm_wr32(device, 0x00403c, ram->coef);
/* fall through */ fallthrough;
default: default:
nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl);
nvkm_wr32(device, 0x004024, ram->coef); nvkm_wr32(device, 0x004024, ram->coef);

2
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
View File

@ -159,7 +159,7 @@ mxm_dcb_sanitise_entry(struct nvkm_bios *bios, void *data, int idx, u16 pdcb)
break; break;
case 0x0e: /* eDP, falls through to DPint */ case 0x0e: /* eDP, falls through to DPint */
ctx.outp[1] |= 0x00010000; ctx.outp[1] |= 0x00010000;
/* fall through */ fallthrough;
case 0x07: /* DP internal, wtf is this?? HP8670w */ case 0x07: /* DP internal, wtf is this?? HP8670w */
ctx.outp[1] |= 0x00000004; /* use_power_scripts? */ ctx.outp[1] |= 0x00000004; /* use_power_scripts? */
type = DCB_CONNECTOR_eDP; type = DCB_CONNECTOR_eDP;