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arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states

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Add device bindings for cpuidle states for cpu devices.

msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
the same microarchitecture and the two clusters only differ in the
maximum frequency attainable by the CPUs.

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This commit is contained in:
Amit Kucheria 2019-05-21 15:05:16 +05:30 committed by Andy Gross
parent 4c9e5dfb45
commit f6aee7af59
1 changed files with 17 additions and 0 deletions
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17
arch/arm64/boot/dts/qcom/msm8996.dtsi
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@ -102,6 +102,7 @@ CPU0: cpu@0 {
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@ -114,6 +115,7 @@ CPU1: cpu@1 {
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
};
@ -122,6 +124,7 @@ CPU2: cpu@100 {
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@ -134,6 +137,7 @@ CPU3: cpu@101 {
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_1>;
};
@ -158,6 +162,19 @@ core1 {
};
};
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <40>;
exit-latency-us = <80>;
min-residency-us = <300>;
};
};
};
thermal-zones {