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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: KVM: Implement vgic-v3 save/restore
Implement the vgic-v3 save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier
parent
3c13b8f435
commit
f68d2b1b73
@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += vgic-v3-sr.o
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@ -32,5 +32,8 @@
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void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
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void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
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void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
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void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
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#endif /* __ARM64_KVM_HYP_H__ */
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226
arch/arm64/kvm/hyp/vgic-v3-sr.c
Normal file
226
arch/arm64/kvm/hyp/vgic-v3-sr.c
Normal file
@ -0,0 +1,226 @@
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/*
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* Copyright (C) 2012-2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/compiler.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_mmu.h>
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#include "hyp.h"
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#define vtr_to_max_lr_idx(v) ((v) & 0xf)
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#define vtr_to_nr_pri_bits(v) (((u32)(v) >> 29) + 1)
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#define read_gicreg(r) \
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({ \
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u64 reg; \
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asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \
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reg; \
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})
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#define write_gicreg(v,r) \
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do { \
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u64 __val = (v); \
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asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
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} while (0)
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/* vcpu is already in the HYP VA space */
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void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
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u64 val;
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u32 max_lr_idx, nr_pri_bits;
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/*
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* Make sure stores to the GIC via the memory mapped interface
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* are now visible to the system register interface.
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*/
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dsb(st);
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cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
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cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
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cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
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cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
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write_gicreg(0, ICH_HCR_EL2);
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val = read_gicreg(ICH_VTR_EL2);
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max_lr_idx = vtr_to_max_lr_idx(val);
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nr_pri_bits = vtr_to_nr_pri_bits(val);
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switch (max_lr_idx) {
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case 15:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(15)] = read_gicreg(ICH_LR15_EL2);
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case 14:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(14)] = read_gicreg(ICH_LR14_EL2);
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case 13:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(13)] = read_gicreg(ICH_LR13_EL2);
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case 12:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(12)] = read_gicreg(ICH_LR12_EL2);
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case 11:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(11)] = read_gicreg(ICH_LR11_EL2);
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case 10:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(10)] = read_gicreg(ICH_LR10_EL2);
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case 9:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(9)] = read_gicreg(ICH_LR9_EL2);
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case 8:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(8)] = read_gicreg(ICH_LR8_EL2);
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case 7:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(7)] = read_gicreg(ICH_LR7_EL2);
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case 6:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(6)] = read_gicreg(ICH_LR6_EL2);
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case 5:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(5)] = read_gicreg(ICH_LR5_EL2);
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case 4:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(4)] = read_gicreg(ICH_LR4_EL2);
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case 3:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)] = read_gicreg(ICH_LR3_EL2);
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case 2:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)] = read_gicreg(ICH_LR2_EL2);
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case 1:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)] = read_gicreg(ICH_LR1_EL2);
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case 0:
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cpu_if->vgic_lr[VGIC_V3_LR_INDEX(0)] = read_gicreg(ICH_LR0_EL2);
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}
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switch (nr_pri_bits) {
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case 7:
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cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
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cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
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case 6:
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cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
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default:
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cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
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}
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switch (nr_pri_bits) {
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case 7:
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cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
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cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
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case 6:
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cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
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default:
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cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
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}
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val = read_gicreg(ICC_SRE_EL2);
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write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
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isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
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write_gicreg(1, ICC_SRE_EL1);
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}
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void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
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{
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struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
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u64 val;
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u32 max_lr_idx, nr_pri_bits;
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/*
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* VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
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* Group0 interrupt (as generated in GICv2 mode) to be
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* delivered as a FIQ to the guest, with potentially fatal
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* consequences. So we must make sure that ICC_SRE_EL1 has
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* been actually programmed with the value we want before
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* starting to mess with the rest of the GIC.
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*/
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write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1);
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isb();
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write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
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write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
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val = read_gicreg(ICH_VTR_EL2);
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max_lr_idx = vtr_to_max_lr_idx(val);
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nr_pri_bits = vtr_to_nr_pri_bits(val);
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switch (nr_pri_bits) {
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case 7:
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write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
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write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
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default:
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write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
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}
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switch (nr_pri_bits) {
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case 7:
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write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
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write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
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default:
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write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
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}
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switch (max_lr_idx) {
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case 15:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(15)], ICH_LR15_EL2);
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case 14:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(14)], ICH_LR14_EL2);
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case 13:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(13)], ICH_LR13_EL2);
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case 12:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(12)], ICH_LR12_EL2);
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case 11:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(11)], ICH_LR11_EL2);
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case 10:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(10)], ICH_LR10_EL2);
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case 9:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(9)], ICH_LR9_EL2);
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case 8:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(8)], ICH_LR8_EL2);
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case 7:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(7)], ICH_LR7_EL2);
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case 6:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(6)], ICH_LR6_EL2);
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case 5:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(5)], ICH_LR5_EL2);
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case 4:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(4)], ICH_LR4_EL2);
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case 3:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)], ICH_LR3_EL2);
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case 2:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)], ICH_LR2_EL2);
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case 1:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)], ICH_LR1_EL2);
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case 0:
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write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(0)], ICH_LR0_EL2);
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}
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/*
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* Ensures that the above will have reached the
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* (re)distributors. This ensure the guest will read the
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* correct values from the memory-mapped interface.
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*/
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isb();
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dsb(sy);
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/*
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* Prevent the guest from touching the GIC system registers if
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* SRE isn't enabled for GICv3 emulation.
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*/
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if (!cpu_if->vgic_sre) {
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write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
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ICC_SRE_EL2);
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}
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}
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u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
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{
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return read_gicreg(ICH_VTR_EL2);
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}
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