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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915: Make i915_engine_info pretty printer to standalone
We can use drm_printer to hide the differences between printk and seq_printf, and so make the i915_engine_info pretty printer able to be called from different contexts and not just debugfs. For instance, I want to use the pretty printer to debug kselftests. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171009110301.21705-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
This commit is contained in:
Chris Wilson
parent
bef27bdb6c
commit
f636edb214
@ -3292,9 +3292,9 @@ static int i915_display_info(struct seq_file *m, void *unused)
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static int i915_engine_info(struct seq_file *m, void *unused)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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struct i915_gpu_error *error = &dev_priv->gpu_error;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct drm_printer p;
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intel_runtime_pm_get(dev_priv);
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@ -3303,149 +3303,9 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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seq_printf(m, "Global active requests: %d\n",
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dev_priv->gt.active_requests);
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for_each_engine(engine, dev_priv, id) {
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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struct drm_i915_gem_request *rq;
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struct rb_node *rb;
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u64 addr;
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seq_printf(m, "%s\n", engine->name);
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seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n",
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intel_engine_get_seqno(engine),
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intel_engine_last_submit(engine),
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engine->hangcheck.seqno,
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jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
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engine->timeline->inflight_seqnos);
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seq_printf(m, "\tReset count: %d\n",
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i915_reset_engine_count(error, engine));
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rcu_read_lock();
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seq_printf(m, "\tRequests:\n");
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rq = list_first_entry(&engine->timeline->requests,
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struct drm_i915_gem_request, link);
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if (&rq->link != &engine->timeline->requests)
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print_request(m, rq, "\t\tfirst ");
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rq = list_last_entry(&engine->timeline->requests,
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struct drm_i915_gem_request, link);
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if (&rq->link != &engine->timeline->requests)
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print_request(m, rq, "\t\tlast ");
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rq = i915_gem_find_active_request(engine);
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if (rq) {
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print_request(m, rq, "\t\tactive ");
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seq_printf(m,
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"\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
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rq->head, rq->postfix, rq->tail,
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rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
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rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
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}
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seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
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I915_READ(RING_START(engine->mmio_base)),
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rq ? i915_ggtt_offset(rq->ring->vma) : 0);
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seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n",
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I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
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rq ? rq->ring->head : 0);
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seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n",
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I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
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rq ? rq->ring->tail : 0);
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seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n",
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I915_READ(RING_CTL(engine->mmio_base)),
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I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
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rcu_read_unlock();
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addr = intel_engine_get_active_head(engine);
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seq_printf(m, "\tACTHD: 0x%08x_%08x\n",
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upper_32_bits(addr), lower_32_bits(addr));
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addr = intel_engine_get_last_batch_head(engine);
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seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
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upper_32_bits(addr), lower_32_bits(addr));
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if (i915_modparams.enable_execlists) {
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const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
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struct intel_engine_execlists * const execlists = &engine->execlists;
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u32 ptr, read, write;
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unsigned int idx;
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seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
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I915_READ(RING_EXECLIST_STATUS_LO(engine)),
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I915_READ(RING_EXECLIST_STATUS_HI(engine)));
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ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
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read = GEN8_CSB_READ_PTR(ptr);
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write = GEN8_CSB_WRITE_PTR(ptr);
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seq_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
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read, execlists->csb_head,
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write,
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intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
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yesno(test_bit(ENGINE_IRQ_EXECLIST,
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&engine->irq_posted)));
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if (read >= GEN8_CSB_ENTRIES)
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read = 0;
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if (write >= GEN8_CSB_ENTRIES)
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write = 0;
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if (read > write)
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write += GEN8_CSB_ENTRIES;
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while (read < write) {
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idx = ++read % GEN8_CSB_ENTRIES;
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seq_printf(m, "\tExeclist CSB[%d]: 0x%08x [0x%08x in hwsp], context: %d [%d in hwsp]\n",
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idx,
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I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
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hws[idx * 2],
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I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)),
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hws[idx * 2 + 1]);
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}
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rcu_read_lock();
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for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
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unsigned int count;
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rq = port_unpack(&execlists->port[idx], &count);
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if (rq) {
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seq_printf(m, "\t\tELSP[%d] count=%d, ",
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idx, count);
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print_request(m, rq, "rq: ");
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} else {
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seq_printf(m, "\t\tELSP[%d] idle\n",
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idx);
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}
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}
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rcu_read_unlock();
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spin_lock_irq(&engine->timeline->lock);
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for (rb = execlists->first; rb; rb = rb_next(rb)) {
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struct i915_priolist *p =
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rb_entry(rb, typeof(*p), node);
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list_for_each_entry(rq, &p->requests,
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priotree.link)
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print_request(m, rq, "\t\tQ ");
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}
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spin_unlock_irq(&engine->timeline->lock);
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} else if (INTEL_GEN(dev_priv) > 6) {
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seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
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I915_READ(RING_PP_DIR_BASE(engine)));
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seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
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I915_READ(RING_PP_DIR_BASE_READ(engine)));
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seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
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I915_READ(RING_PP_DIR_DCLV(engine)));
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}
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spin_lock_irq(&b->rb_lock);
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for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
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struct intel_wait *w = rb_entry(rb, typeof(*w), node);
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seq_printf(m, "\t%s [%d] waiting for %x\n",
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w->tsk->comm, w->tsk->pid, w->seqno);
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}
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spin_unlock_irq(&b->rb_lock);
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seq_puts(m, "\n");
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}
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p = drm_seq_file_printer(m);
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for_each_engine(engine, dev_priv, id)
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intel_engine_dump(engine, &p);
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intel_runtime_pm_put(dev_priv);
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@ -22,6 +22,8 @@
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*
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*/
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#include <drm/drm_print.h>
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#include "i915_drv.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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@ -1616,6 +1618,164 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
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}
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}
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static void print_request(struct drm_printer *m,
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struct drm_i915_gem_request *rq,
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const char *prefix)
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{
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drm_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
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rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
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rq->priotree.priority,
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jiffies_to_msecs(jiffies - rq->emitted_jiffies),
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rq->timeline->common->name);
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}
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void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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struct i915_gpu_error *error = &engine->i915->gpu_error;
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_gem_request *rq;
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struct rb_node *rb;
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u64 addr;
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drm_printf(m, "%s\n", engine->name);
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drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n",
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intel_engine_get_seqno(engine),
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intel_engine_last_submit(engine),
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engine->hangcheck.seqno,
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jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
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engine->timeline->inflight_seqnos);
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drm_printf(m, "\tReset count: %d\n",
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i915_reset_engine_count(error, engine));
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rcu_read_lock();
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drm_printf(m, "\tRequests:\n");
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rq = list_first_entry(&engine->timeline->requests,
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struct drm_i915_gem_request, link);
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if (&rq->link != &engine->timeline->requests)
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print_request(m, rq, "\t\tfirst ");
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rq = list_last_entry(&engine->timeline->requests,
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struct drm_i915_gem_request, link);
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if (&rq->link != &engine->timeline->requests)
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print_request(m, rq, "\t\tlast ");
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rq = i915_gem_find_active_request(engine);
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if (rq) {
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print_request(m, rq, "\t\tactive ");
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drm_printf(m,
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"\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
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rq->head, rq->postfix, rq->tail,
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rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
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rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
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}
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drm_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
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I915_READ(RING_START(engine->mmio_base)),
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rq ? i915_ggtt_offset(rq->ring->vma) : 0);
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drm_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n",
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I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
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rq ? rq->ring->head : 0);
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drm_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n",
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I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
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rq ? rq->ring->tail : 0);
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drm_printf(m, "\tRING_CTL: 0x%08x [%s]\n",
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I915_READ(RING_CTL(engine->mmio_base)),
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I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
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rcu_read_unlock();
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addr = intel_engine_get_active_head(engine);
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drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
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upper_32_bits(addr), lower_32_bits(addr));
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addr = intel_engine_get_last_batch_head(engine);
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drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
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upper_32_bits(addr), lower_32_bits(addr));
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if (i915_modparams.enable_execlists) {
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const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
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struct intel_engine_execlists * const execlists = &engine->execlists;
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u32 ptr, read, write;
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unsigned int idx;
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drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
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I915_READ(RING_EXECLIST_STATUS_LO(engine)),
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I915_READ(RING_EXECLIST_STATUS_HI(engine)));
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ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
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read = GEN8_CSB_READ_PTR(ptr);
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write = GEN8_CSB_WRITE_PTR(ptr);
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drm_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
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read, execlists->csb_head,
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write,
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intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
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yesno(test_bit(ENGINE_IRQ_EXECLIST,
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&engine->irq_posted)));
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if (read >= GEN8_CSB_ENTRIES)
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read = 0;
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if (write >= GEN8_CSB_ENTRIES)
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write = 0;
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if (read > write)
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write += GEN8_CSB_ENTRIES;
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while (read < write) {
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idx = ++read % GEN8_CSB_ENTRIES;
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drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [0x%08x in hwsp], context: %d [%d in hwsp]\n",
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idx,
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I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
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hws[idx * 2],
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I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)),
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hws[idx * 2 + 1]);
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}
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rcu_read_lock();
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for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
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unsigned int count;
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rq = port_unpack(&execlists->port[idx], &count);
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if (rq) {
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drm_printf(m, "\t\tELSP[%d] count=%d, ",
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idx, count);
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print_request(m, rq, "rq: ");
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} else {
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drm_printf(m, "\t\tELSP[%d] idle\n",
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idx);
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}
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}
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rcu_read_unlock();
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spin_lock_irq(&engine->timeline->lock);
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for (rb = execlists->first; rb; rb = rb_next(rb)) {
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struct i915_priolist *p =
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rb_entry(rb, typeof(*p), node);
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list_for_each_entry(rq, &p->requests,
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priotree.link)
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print_request(m, rq, "\t\tQ ");
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}
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spin_unlock_irq(&engine->timeline->lock);
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} else if (INTEL_GEN(dev_priv) > 6) {
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drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
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I915_READ(RING_PP_DIR_BASE(engine)));
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drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
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I915_READ(RING_PP_DIR_BASE_READ(engine)));
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drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
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I915_READ(RING_PP_DIR_DCLV(engine)));
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}
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spin_lock_irq(&b->rb_lock);
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for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
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struct intel_wait *w = rb_entry(rb, typeof(*w), node);
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drm_printf(m, "\t%s [%d] waiting for %x\n",
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w->tsk->comm, w->tsk->pid, w->seqno);
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}
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spin_unlock_irq(&b->rb_lock);
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drm_printf(m, "\n");
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftests/mock_engine.c"
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#endif
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@ -7,6 +7,8 @@
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#include "i915_gem_timeline.h"
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#include "i915_selftest.h"
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struct drm_printer;
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#define I915_CMD_HASH_ORDER 9
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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@ -839,4 +841,6 @@ void intel_engines_reset_default_submission(struct drm_i915_private *i915);
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bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
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void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p);
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#endif /* _INTEL_RINGBUFFER_H_ */
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