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STAGING: Octeon: Set SSO group mask properly on CN68XX
CN68XX uses SSO instead of POW. Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10966/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -172,9 +172,16 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
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}
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/* Only allow work for our group (and preserve priorities) */
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old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
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cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
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(old_group_mask & ~0xFFFFull) | 1 << pow_receive_group);
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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old_group_mask = cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid));
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cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid),
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1ull << pow_receive_group);
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cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */
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} else {
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old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
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cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
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(old_group_mask & ~0xFFFFull) | 1 << pow_receive_group);
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}
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if (USE_ASYNC_IOBDMA) {
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cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
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@ -397,7 +404,13 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
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}
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}
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/* Restore the original POW group mask */
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cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), old_group_mask);
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cvmx_read_csr(CVMX_SSO_PPX_GRP_MSK(coreid)); /* Flush */
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} else {
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cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
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}
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if (USE_ASYNC_IOBDMA) {
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/* Restore the scratch area */
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cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
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